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Discussion Qualcomm Snapdragon Thread

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And, here I thought Apple's E-cores were king in performance per area, but if you look at that graph you'll see that Oryon-M has similar die area while mustering much better performance. Still, it says nothing about power usage. It clearly gets there by virtue of high clock frequency.
 
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And, here I thought Apple's E-cores were king in performance per area, but if you look at that graph you'll see that Oryon-M has similar die area will mustering much better performance. Still, it says nothing about power usage. It clearly gets there by virtue of high clock frequency.
Qualcomm's Ms are closer to what Apple showed with M5 Pro/Max "performance" cores tbh. Apple's littles don't clock all that high.
 
I don't think it's just that. It's a combination of multiple factors:
- Until 2024, Apple's performance cores were really the only ones in their weight class. Arm first introduced the X-series back in 2021, but it wasn't until X925 that they designed a comparable core in terms of execution resources and area constraints. And Qualcomm introduced Phoenix back in 2024.
- Apple were the only ones to use N3B, which saw a big clock speed bump (I think they went from 3.49 to 4.05 in one gen). Everyone else was spoked by the N3 issues and made the jump a year later in 2024 with N3E (X925/Phoenix). As soon as they did that, they made a similar clock speed jump.
View attachment 140251
Qualcomm's Oryon G2-L cores are 2/3 the size of Apple's. That sounds like great area savings, but this means they are a gen behind Apple in peak ST performance, and about 2 gets behind in ST efficiency. Why don't they build a bigger core?
 
Qualcomm's Ms are closer to what Apple showed with M5 Pro/Max "performance" cores tbh. Apple's littles don't clock all that high.
If we consider Oryon V3-M, it seems it sits between Apple's E and 'P' cores.

Oryon V2 (according to your chart);
L = 100%
M = 58%

Oryon V3 (according to Geekerwan's 8E G5 review);
L = 100%
M = ~ 50%

Apple M5 cores (according to ColorScale video);
S = 100%
P = 70%
E = 40%
 
What I don't get is how the X2 Elite Extreme is being handily beaten by M5 Max in Geekbench nT.

X2EE = 23.5k
M5 Max = 29k

Even if we account for the Windows tax, that puts X2EE at about 26k (if it runs in Linux). Still 3k points is a substantial gap.

As I understand it, the way Geekbench 6 nT test scales, it favours fewer strong cores over lots of weak cores.

X2EE and M5 Max both have the same core count, but X2EE has the bulkier 12L+6M configuration, which Geekbench should like more than the 6S+12P of M5 Max, surely?
 
What I don't get is how the X2 Elite Extreme is being handily beaten by M5 Max in Geekbench nT.

X2EE = 23.5k
M5 Max = 29k

Even if we account for the Windows tax, that puts X2EE at about 26k (if it runs in Linux). Still 3k points is a substantial gap.

As I understand it, the way Geekbench 6 nT test scales, it favours fewer strong cores over lots of weak cores.

X2EE and M5 Max both have the same core count, but X2EE has the bulkier 12L+6M configuration, which Geekbench should like more than the 6S+12P of M5 Max, surely?

Its memory bandwidth is ~3x higher than X2EE.

I suspect that the chiplet design of M5 Max results in better thermals and less throttling for its CPU tile as well...
 
What I don't get is how the X2 Elite Extreme is being handily beaten by M5 Max in Geekbench nT.

X2EE = 23.5k
M5 Max = 29k

Even if we account for the Windows tax, that puts X2EE at about 26k (if it runs in Linux). Still 3k points is a substantial gap.

As I understand it, the way Geekbench 6 nT test scales, it favours fewer strong cores over lots of weak cores.

X2EE and M5 Max both have the same core count, but X2EE has the bulkier 12L+6M configuration, which Geekbench should like more than the 6S+12P of M5 Max, surely?
My guess is the Snapdragon chip throttles more. According to the specsheet, the X2 Elite Extreme prime cores can do 5Ghz in single thread, but only 4.4Ghz in multi-thread.
 
The Case for a Unified Qualcomm SoC: Bridging Mobile and PC

The strategy of repurposing mobile silicon for larger form factors—as seen with MediaTek’s Kompanio line or Apple's Macbook Neo—presents a compelling roadmap for Qualcomm. By utilizing a common die across both smartphones and PCs, Qualcomm could fundamentally shift its competitive position in the PC landscape.

Potential Benefits

Lower Production Costs:
By using the same dies for mobile and PC chips, Qualcomm can leverage massive economies of scale, minimize R&D costs, and improve time to market.

Annual Upgrade Cadence: Smartphone chips receive yearly refreshes. Adopting a unified die strategy would enable Qualcomm to deliver yearly chip upgrades for the PC market, allowing them to remain competitive with the annual release cycles of Apple Silicon and Intel. This would be less economical if Qualcomm taped out seperate dies solely for PCs, since their PC volume is small.

Potential Disadvantages

The primary hurdle is "wasted die area". There are differences between the requirements of PCs and smartphones.

Smartphone Chips: Require an integrated modem for power efficiency and a large ISP (Image Signal Processor) to handle complex mobile photography.

PC Chips: Demand expanded I/O (more USB and PCIe lanes) and additional display controllers to support multiple high-resolution external monitors.

Including PC-specific I/O on a phone chip, or a massive ISP on a laptop chip, creates "dead weight" on the silicon that increases costs without adding value to the specific device.

One way to mitigate the "wasted area" is to move the cellular modem off-chip. While integrated modems are traditionally superior for power management, multiple generations of iPhones have proven that Qualcomm’s external modems are exceptionally high caliber. Even as Apple transitions to in-house silicon, their custom modems (such as the C1) remain external. Reports suggest Apple may eventually merge their N-series (Wi-Fi/Bluetooth) and C-series (5G) into a single connectivity chip.

Qualcomm could adopt a similar modular approach. By removing the modem from the primary SoC and integrating it into their FastConnect (Wi-Fi/Bluetooth) chip, they could create a universal SoC die for both PCs and smartphones. Hardware configurations would then be determined by the secondary connectivity chip:

PC Configuration: SoC + FastConnect (Wi-Fi + BT)

Phone Configuration: SoC + FastConnect (Wi-Fi + BT + Cellular)

How would this SoC setup work in practice?

SoC dieExample configMobilePC
Die 12L+6M CPU

3 slice GPU
8 series

(for phones/
tablets)
X# Plus

(for budget laptops)
Die 26L+6M CPU

5 slice GPU
9 series
(for tablets)
X# Elite

(for premium ultrabooks)

It doesn't make sense for high end PC chips like X# Elite Extreme to share common dies with phones/tablets. So those will have to use seperate dies for solely that purpose, and might have to stick a 2 year release cycle.

This whole post has been written assuming the SoCs are monolithic. I didn't mention chiplets, which opens a whole new sea of possibilities.


 
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