Processor Differences

[Xenocide187]

I admit that I don't really know much about the apple, but recently I have been thinking about its hardware. What are the differences between Apple processors and PC processors? Why are its speeds lower compared to PCs? Is it 32 or 64 bit processing? How does it process information (is it different from PC processors)?

Any information on it would be great, it doesn't have to be the questions I asked.

 

[cquark]

Originally posted by: Xenocide187
I admit that I don't really know much about the apple, but recently I have been thinking about its hardware. What are the differences between Apple processors and PC processors? Why are its speeds lower compared to PCs? Is it 32 or 64 bit processing? How does it process information (is it different from PC processors)?

Any information on it would be great, it doesn't have to be the questions I asked.

Older PowerPCs are 32-bit; current ones like the PPC 970 are 64-bit processors. Both are modern superscalar designs that process information in essentially the same way, though of course, they have different instruction sets.

PowerPCs run at slower clock speeds for similar reasons as to why AMD processors run at lower clock speeds than Intel's P4: their architectural decisions were focused on performance through doing more tasks per clock cycle rather than through higher clock cycles. One easily observable architectural difference resulting from this choice is pipeline length, with the Prescott P4 having over 30 stages while current PowerPCs have about a third that many.

As Intel couldn't ramp their clock speeds as desired last year (weren't able to break 4GHz) due to leakage current issues, IBM and AMD's decisions seem wiser in retrospect.

Ars Technica has some great papers on these topics:

A History of PowerPC on Apple
http://arstechnica.com/articles/paedia/cpu/ppc-1.ars/1

Comparison of Intel P4 and PowerPC G4e
http://arstechnica.com/article...dia/cpu/p4andg4e.ars/1

 

[Calin]

One thing I know for sure is that the recent Apple processors are derived from the IBM Power processors (G4, G5). Some of them have the Altivec instruction set, which is a Single Instruction Multiple Data instruction set, allowing vector processing faster than with normal operations.
Why are the speeds lower? More complexity in the silicon, or more complexity in the internal traces. However, lower speeds could be higher performance, compare the Pentium 4 2.0 GHz with the Athlon 64 2.0 GHz (this being a 3000+ processor).
The Apple changed their entire processor line when going from the 68040 processors to the Power derived processors (PowerMac, PowerPC, ...). Apple win that change, unlike Intel with their intended move to Itanium (however the opportunities for success were much bigger on the Apple side).
If I remember correctly, the Intel processors (8086 and later) store number with the least significant bit first. Motorola processors (680x0) stored the most significant bit first, and the POWER processors were capable to operate in either way (to help the transition to the new Power processors on the Mac). The old programs for the Macintosh were run with a software emulation thingy, running slower on the new computers than on the older ones. However, the programs that made the Apple world go round were quickly rewritten, and the new architecture was more capable of higher processor speeds, had faster memory and faster and wider connections between processor and the rest of the system.

 

[bobdole369]

Big-Endian vs. Little-Endian are the names for the concept described (least significant vs. most significant bit stored first)

 

[Bassyhead]

Another big difference between the PowerPC and x86 ISAs (instruction set architectures) is that the PowerPC is a RISC and is a load-store ISA while x86 is a CISC (though the CPU might still interpret x86 instructions into RISC-like microinstructions) and is a register-memory ISA. Their instruction sets and inner workings (registers, datapaths, memory access, etc) are very different. RISC machines usually have fewer instructions that are simpler which also makes the CPU easier to design. CISC machines typically have lots of addressing modes and greater complexity on the CPU level.

 

[fitten]

Big/Little endian isn't about bits, it's about byte storage order.

The terms "RISC" an "CISC" have been blurred a whole lot to the point of being meaningless now. RISC ISAs were predominately load/store, as you say. Loading and storing data from/to memory is seperate from actually manipulating the data (add, subtract, etc.). CISC had memory-memory operations where loading data was a part of the addressing mode of the instruction.

Initially, RISC vs. CISC has some discussion about a reduced number of valid instructions in the ISA but this hasn't been true in quite a while. For example, if you count the number of valid instructions on the P4 (including SSE2 and the like) and compare that with the number of instructions available to a G4 (PPC, including AltiVec), you'll actually see that the G4 (supposedly RISC) has more instructions than the P4 (supposedly CISC).

Traditional "RISC" and "CISC" really don't apply much anymore when discussing ISAs.