Problems with TSMC 40nm?

[thilanliyan]

http://www.theinquirer.net/inq...878/tsmc-40nm-revealed

Omg no nVidia rant!!!

 

[Keysplayr]

ATI and NV might just stick to 55nm if 40nm is a nightmare. Who knows. It pretty much always works out eventually though.

 

[nosfe]

he didn't say that its a nightmare, just not to expect 1.5x performance increase or lower power/heat from the cards. If its only leakage then yields shouldn't be affected so the price of the first 40nm cards should be quite low considering that they won't have many changes made to them compared to their 55nm counterparts

 

[SlowSpyder]

I am more likely to believe this story as it's not another anti-Nvidia rant... I half expected them to say that only 40nm wasn't working for Nvidia after are I started reading the story.

I'm sure both AMD and Nvidia had to know that this could be an issue since it is the newest of the new technology. I wonder if it'd be too hard/any benefit to going with 45nm now, assuming that works better, then introduce 40nm a bit later as a slightly higher line.

Then again, it is the Inq and we could see 40nm in Spring and everything might be fine.

 

[Idontcare]

Originally posted by: SlowSpyder
I am more likely to believe this story as it's not another anti-Nvidia rant... I half expected them to say that only 40nm wasn't working for Nvidia after are I started reading the story.

You can believe the story insofar as it relates to TSMC's current debacle with 40nm...its the same debacle they were having a year ago when they were still calling it the 45nm node.

Then it (45nm) became so delayed that they re-labeled it as the 40nm node (hey look, we are now back on schedule!) but after spending the past 12 months frantically trying to tweak the processes to hit spice model targets without killing Iddq they are finally getting close but they are most definitely still facing challenges.

Mind you the other foundries are in even a worse of a pickle. UMC, Chartered, and IBM are all struggling to get 45nm (or 40nm for those that have re-labeled) off the ground and into volume production.

It just sounds sexier to say you are producing 40nm with slight delays versus saying you are still struggling to get a much delayed 45nm into volume production. And the 45nm -> 40nm relabel incurred the knock-on effect of shuffling all successive nodes down by one half-node increment.

What was going to be 40nm has been re-badged as the 32nm node and pushed out two years. What was going to be 32nm is now label 28nm and pushed out 2 yrs from the original 32nm delivery date. What was going to be the 28nm node has been re-badged as the 22nm node and pushed out another two years. (this is for TSMC)

It's all PR, TSMC could label the node the 10nm node for all they wanted, it would make for some sensational headlines for a brief period of time but the customers would still be dealing with the fact they were designing chips to use the same old crappy 40nm xtor parametrics and spice targets.

 

[nZone]

because TSMC doesn't want to buy the implantor
one implantor costs 5-10 mil a pop.

 

[Keysplayr]

Originally posted by: nZone
because TSMC doesn't want to buy the implantor
one implantor costs 5-10 mil a pop.

Implantor. Sounds painful.

 

[Idontcare]

Originally posted by: keysplayr2003

Originally posted by: nZone
because TSMC doesn't want to buy the implantor
one implantor costs 5-10 mil a pop.

Implantor. Sounds painful.

Ha ha! It sure does. He means implanter, as in ion implantation.

And yes, despite having never stuck my hand in front of an ion beam, it seems like a safe assumption that slamming ions of P, As, B, etc into a body part at 500KeV and higher would likely result in a rather painful outcome. :laugh:

 

[nZone]

ha ha...thanks for correcting me..

either they didn't want spend money for new implantER or they didn't want spend any money at all (like $50k for one wafer )

 

[Idontcare]

Originally posted by: nZone
ha ha...thanks for correcting me..

either they didn't want spend money for new implantER or they didn't want spend any money at all (like $50k for one wafer )

Indeed. Given news like this (TSMC's January sales down 59% year-to-year) it is no wonder they won't spot the dough for an implanter.

In fact it might be time to wheel out the old implantor and convince a few TSMC customers that their loyalty needs to be demonstrated by show of a few more orders.

 

[Keysplayr]

Originally posted by: nosfe
he didn't say that its a nightmare, just not to expect 1.5x performance increase or lower power/heat from the cards. If its only leakage then yields shouldn't be affected so the price of the first 40nm cards should be quite low considering that they won't have many changes made to them compared to their 55nm counterparts

Not a nightmare? Do you have any idea how long TSMC has been trying to "perfect" 40nm process? Waaaaay overdue. Waaaay late.

EDIT: Oops, I see Idontcare is on the same page.

 

[KingstonU]

Inquirer's explanation that TSMC has a 'cunning plan' to stop the leakage (via youtube link) is hilarious! :laugh:

 

[eklock2000]

So bottom line, don't hold your breath for a 40nm part and go with an X2 or 295...or is it too early to tell?

I thought an implanter was someone who worked on Pamela Anderson

...the outcome is more "tangible" anyways.

EK2K

 

[Idontcare]

Originally posted by: KingstonU
Inquirer's explanation that TSMC has a 'cunning plan' to stop the leakage (via youtube link) is hilarious! :laugh:

Lucy! You gots some splain'ens to dues!

Originally posted by: keysplayr2003

Originally posted by: nosfe
he didn't say that its a nightmare, just not to expect 1.5x performance increase or lower power/heat from the cards. If its only leakage then yields shouldn't be affected so the price of the first 40nm cards should be quite low considering that they won't have many changes made to them compared to their 55nm counterparts

Not a nightmare? Do you have any idea how long TSMC has been trying to "perfect" 40nm process? Waaaaay overdue. Waaaay late.

EDIT: Oops, I see Idontcare is on the same page.

Yeah but you manage to put into a sentence what takes me paragraphs to communicate. So keep it up! Everyone else suffers if they have to keep reading my novels just to get to the point

 

[Cookie Monster]

I always thought the 40nm process tech was ahead of schedule.

Bottom line is, this doesn't sound too good for ATI since it doesn't really offer them much but good for nVIDIA in the sense that they can further shrink their godzilla chips.

 

[CountZero]

Wish there was a quoted credible source to back this up not to mention more information than leakage power is high.

If TSMC is giving out models that don't accurately reflect what the process can do that is a serious issue.

If they are giving out accurate models and it just turns out 40nm sucks from a power perspective well that sucks but it isn't necessarily surprising and wouldn't be at all surprising to any company planning to use that process.

 

[nosfe]

Originally posted by: Cookie Monster
I always thought the 40nm process tech was ahead of schedule.

Bottom line is, this doesn't sound too good for ATI since it doesn't really offer them much but good for nVIDIA in the sense that they can further shrink their godzilla chips.

no, they can't, leakage problems mean that a 40nm gt200 would produce much more heat than it does now. It should work fine with small chips because smaller dies mean less leakage which is one of the reasons why both ati and nvidia are first introducing cheapo 40nm cards as i'm sure they knew well before Charlie about this, if it's true, of course

 

[VirtualLarry]

Speaking of leakage, that's my guess as to why some of my CPUs get so hot, at not-so-high voltages.

Isn't it true that leaky transistors tend to be faster transistors, insomuch that transistors designed to stop leakage, are generally slower?

 

[Idontcare]

Originally posted by: CountZero
Wish there was a quoted credible source to back this up not to mention more information than leakage power is high.

If TSMC is giving out models that don't accurately reflect what the process can do that is a serious issue.

If they are giving out accurate models and it just turns out 40nm sucks from a power perspective well that sucks but it isn't necessarily surprising and wouldn't be at all surprising to any company planning to use that process.

Yeah your not going to get a credible source to confirm this. Credible would be someone with proof in hand, and the only way to get proof in hand is to sign legal contracts which, among other things, are designed to prevent you from divulging conclusive evidence on embarrassing things like this.

 

[dajeepster]

Originally posted by: VirtualLarry

Isn't it true that leaky transistors tend to be faster transistors, insomuch that transistors designed to stop leakage, are generally slower?

in simple terms... leaky transistors seem to be faster because your not fully shutting them off.... leaky transistor cause more power loss since more current goes through than is intended or wanted.... pwrloss=resistance*(current^2)... so more current, more loss... equates to bad juju... kinda like the pentium IVs

 

[Idontcare]

Originally posted by: VirtualLarry
Speaking of leakage, that's my guess as to why some of my CPUs get so hot, at not-so-high voltages.

Isn't it true that leaky transistors tend to be faster transistors, insomuch that transistors designed to stop leakage, are generally slower?

http://en.wikipedia.org/wiki/MOSFET

Leaky(ier) transistors will be faster(er) transistors if, for example, the primary contributing source to the elevated leakage stems from gate leakage because the gate has intentionally been thinned (allowing exponentially higher levels of leakage current) so as to decrease the gate's electric field propagation time into the channel.

The majority of other forms of leakage are also necessary evils in that eliminating them as a leakage source would require engineering the transistor in such a way that would indeed negatively impact the transistor's switching speed (gate to drain spacer thickness for example) but the technical cause of the leakage does not necessary also induce an increase in performance.

It's complicated to put it mildly and I am way oversimplifying the situation here. I'm sure others can pitch in and give more examples where higher leakage is an unavoidable consequence of the device physics being optimized for faster xtor switching speeds.

 

[magreen]

So this bodes well for The Foundry Company, which has already perfected 45nm, does it not?

(Idc, nice to see you over here helping make the video forum a better place )

 

[Idontcare]

Originally posted by: magreen
So this bodes well for The Foundry Company, which has already perfected 45nm, does it not?

(Idc, nice to see you over here helping make the video forum a better place )

Without a doubt TFC's xtor parametrics are going to be zippier than what TSMC is fielding, but they are also SOI-based and (for a myriad of design related reasons) can't be compared to TSMC's 45nm (or 40nm) xtors on an apples-to-apples basis.

There are industry standards for normalizing xtor parametrics in a way that does lend themselves to apples-to-apples comparison, e.g. casting Idrive into length normalized values (micro-amps per micron) at a standardized voltage (1.0V).

These numbers do get reported at the appropriate conferences (IEDM for example). This graph is a perfect example.

But you have to consider that TFC's 45nm process are essentially solely optimized for high-performance MPU IC's whereas TSMC's processes are tiered into low-power, medium-power, and high-power applications.

You see examples elsewhere in the industry of IDM's doing this, Intel is publicly acknowledging similar tiers to their node structure with their P1266 and P1266.8 breakout at 45nm. At TI we maintained three sub-nodes as well, just as the foundries do.

So while TFC's 45nm xtors are good for exactly what they were engineered to do (make K10.5) they might be really not good for making GPU's for Nvidia/ATI or cellphone chips for Qualcomm and TI.

Since TFC is a foundry we can expect them to diversify their xtor process technology portfolio and expand their services back into bulk-Si as well as offering multiple performance/power-consumption flavors of the node. They really have no choice in the matter if they want to attract customers, but having experience with generating leading edge high-performance MPU process technology definitely gives them a leg-up at time-zero as the high-performance process tech is the hardest to create (hence the timeline lag between Intel and AMD, and likewise between AMD and TSMC).

This video forum seems like a nice enough place already before I started rambling in it. I can't contribute much to the "zomg I get 400fps with my newest quad-xfire rig" threads but these technology discussions play well into my real world experiences so I do hope to be value-add to the forum in that regard.

 

[thilanliyan]

Originally posted by: Idontcare
This video forum seems like a nice enough place already before I started rambling in it.

Hehe...it isn't always nice I assure you.

 

[Extelleron]

It's not good to hear that TSMC's 40nm process is so bad, but it is not unexpected IMO. It is clearly getting harder and harder for the smaller players (TSMC is hardly a small player in the industry, but compared to Intel) to keep up with process development. Especially it is hard for TSMC and others to approach the 45nm node without HKMG. It's not impossible; AMD's 45nm process is very solid w/o HKMG. Aside from performance issues, the development time is taking longer - at this rate it will be ~2 years between when Intel released 45nm chips and when volume production of 40nm chips begins. Intel should have 32nm chips released not long after TSMC reaches their 40nm node, which performance-wise will not come even close to Intel's 45nm (and might even be slower than Intel's 65nm?).

This does leave an opening for The Foundry company to get some business; TFC has a solid 45nm process right now, unfortunately it is limited a bit in its application because of SOI. FC should be releasing 32nm bulk HKMG in 2010, however, so that will likely be usable by most current customers of TSMC. If the Inquirer is accurate about TSMC's 40nm process bringing little to no performance increase, it is likely a lot of those customers (especially ATI / nVidia) will go to TFC instead. TFC will have a solid 32nm process in 2010, at this rate TSMC is likely if they have a 28nm process in 2011.