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Prescott to have deeper pipeline-more changes than most people thought

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paralazarguer

Banned
According to ars the Prescott will have a deeper pipeline to make it more scaleable. It will also sport double the L1 and L2 cache, 13 new instructions, an improved form of hyperthreading, be based on .09u manufacturing process, have x86-64 present in the silicon but disabled an 800mhz FSB, and use socket-T.
I was familiar with most of those specs but the deeper pipeline and socket-T are news to me. They must be calling this thing the Pentium 5. There's nothing left of the Pentium 4 in her....
 
have x86-64 present in the silicon
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could this be a sign that intel is really worried about Hammer? then they could advertise that the pentium 5 is a 64bit processer (like the athlon 64). If the instructions are there, a new revision of the cpu would have them functioning.

Anyone know how compatible AMD's x86-64 and intels yamhill (x86-64) technology is?
 
The Prescott uses a version of Intel's Netburst Architecture, so I can see why they are keeping the Pentium 4 label on it. The Northwood had a cache increase, FSB increase with the 533MHz CPU, introduced HT with the 3.06GHz, die shrink to .13u, and a new socket, but it was still a P4.

Labels like Pentium 4 aren't meant to reflect the technical detail of a processor, but rather the reputation of Intel that has been established with earlier products and practices. BTW, don't forget that Strained Silicon comes on the Prescott too. Peace.
 
Companies selling compilers must love this stuff. Every time anybody releases a new chip they get to sell another round of compilers to take advantage of new instructions.
 
Of course it will have deeper pipelines. How else will they keep ahead in the MHz wars and sell their slower CPU's to all the chumps out there for more money?
 
As far as the Socket-T thing goes, from what I've read, Prescott will intially be released in Socket-478, and then sometime in 2004 it will transition over to Socket-T. So it sounds like there will be Socket-478 upgrade options.
 
Also mentions x86-64 support! HAHA! Intel would have to get a liscense from AMD! Transmeta has already liscensed x86-64 from AMD.

Actuallly the deepend pipeline is not the way to go. Branch misprediction will be too high past the already large 20 stages. I dont think this is such a good idea. We might see the prescott only marginally out perform the Northwood pentium 4 due to high clock speed + bigger
cache. At the same clockspeed or within 200-300 mhz however with a vastly deeper pipeline the prescott core would get trounce by the northwood even with the larger cache. Enhancements might even it out but heck remember pentium 3 beating the pentium 4 out due to the incredible sized pipeline?
 
I can't really comment as to what Prescott will and won't have, other than what Intel has already released.

However, for paralazarguer to say that Prescott will have x86-64 support as if it were fact, is not right. It's just a rumor that's been going around for a long time now. And the article stated that it was "rumored".

And also, I'm not sure where Ars got the idea that Prescott will have stages added to the pipeline. An AnandTech article is linked, but it doesn't say anything of the sort.



Again, I'm not saying that any of the above is necessarily true or not true. Just that it may not be a good idea to state it as a fact, when there is nothing to back it up.
 
And also, I'm not sure where Ars got the idea that Prescott will have stages added to the pipeline. An AnandTech article is linked, but it doesn't say anything of the sort.
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Actually, I've seen a lot of media outlets referring to the pipeline being deepend. In fact, after posting this, I took a look around and was amazed that I didn't see it before.
The pipeline deepening is fact.
"Recent revelations from IDF now tell us that Intel is cranking up the L1 and L2 cache sizes to 16K (d-cache) and 1MB, respectively. They've also deepened the pipeline in order to be able to scale the new core to around 5GHz"
Ars is the man and knows pretty much everything about processor architecture. If he says it's so, I believe him.
 
*confirmed* here's and article from tech report about the deepend pipeline based on a document right from Intel.
TR reader Perezoso tipped us off on an interesting document detailing Intel's upcoming Prescott processor that has made its way onto the web. The document was briefly available on Intel's web site, but it's since been pulled. Thankfully, Sandpile.org has preserved the document in all its glory. What tasty nuggets of information does the document reveal? How about Prescott's key features:
Support for Hyper-Threading (HT) Technology

Prescott New Instructions support

Deeper pipelining to enable higher frequency

A High-speed System Bus
While some of the above information isn't new, the leaked document does explain Prescott's new instructions in detail, with pretty diagrams and everything. The revelation that Prescott will have a deeper pipeline to enable higher frequencies is also new.
Making the Pentium 4's already deep pipeline even deeper should help Intel win over consumers with astronomical clock speeds, but a deeper pipeline will also carry greater branch prediction penalties. Larger caches, a faster system bus and a new branch prediction unit could help Prescott's IPC, but it will likely be months before we know for sure.
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Companies selling compilers must love this stuff. Every time anybody releases a new chip they get to sell another round of compilers to take advantage of new instructions.
Click to expand...
Not really. Microsoft doesn't time visual c++ versions with new instrution sets at all. It took them forever to release a patch that gave SSE support. (and the thing screwed up everything on my computer.)
 
Pentium IV doubles pipeline depth over P6 core, so I doubt there will be too much difference clock for clock with the new Prescott core. Unless, of course, Intel decided 40 stages sounds nice. Either way, the basic layout is the same, just tweaked. Pentium III beating out the Pentium IV involved the lower speed Pentium IV's vs the higher speed Pentium III's as well as twice the pipeline depth and not enough MHz to make up for it.

More cache dosn't make a new name. P6 core had many L2 cache sizes at 0kb, 128kB, 256kB, and 512 kB and 3-4 different names, but each with 2-3 different cache sizes. I think there was a 1MB version of the Pentium Pro, but I don't remember that well. L1, I don't know, simply because I didn't pay attention until Pentium III came out.

13 new instructions doesn't mean entirely new core. Pentium III's major change over Pentium II was KNI. However, MMX on the P5 core didn't require a new brand name. So the 13 instructions may go with a new name, or not.

Socket change doesn't seem to matter, either. Pentium III saw 2 socket changes. Celeron's had its fun with 4, but for a different reason. Pentium 4 has only 1.

All in all, it looks like whether or not Intel calls Prescott the Pentium V is now arbitrary. Intel stopped changing names due to generation when they lost the fight to retain exclusive use of x86 and has since come up with new names as the market requires. If Intel really does rename the new Socket-T chip as Pentium V, it's probably because the market's down and Intel needs to find a reason for people to justify upgrading their dumb terminals.
 
Hey Wingz, is the transition to LGA necessitated by increasing clock speeds? Any other benefits over a the PGA's we're all used to? Just curious!

Kramer
 
Originally posted by: majewski9
Also mentions x86-64 support! HAHA! Intel would have to get a liscense from AMD!
Click to expand...

AMD and Intel have a cross-liscencing agreement for all x86 extensions. Each is free to use the others. Hence, AMD being allowed to provide support for SSE/SSE2/MMX.

Actuallly the deepend pipeline is not the way to go. Branch misprediction will be too high past the already large 20 stages. I dont think this is such a good idea. We might see the prescott only marginally out perform the Northwood pentium 4 due to high clock speed + bigger
cache. At the same clockspeed or within 200-300 mhz however with a vastly deeper pipeline the prescott core would get trounce by the northwood even with the larger cache. Enhancements might even it out but heck remember pentium 3 beating the pentium 4 out due to the incredible sized pipeline?
Click to expand...

Depends on what was extended. Branch and integer instructions are somewhat branchy and Office software that uses this normally suffer a pretty big penalty when it comes to performance on a hyperpipelined design. FP-intensive software, however, is usually not very branchy. It would depend on what type of "deepening" they did to the pipeline. If they just added a few propogation stages, it may or may not hurt too much. If they've redistributed current functions through more stages (would require a dramatic redesign so I doubt it), it may hurt a lot. If they merely added a few stages (to help SSE3 functions) to the FP pipeline, it may not matter much at all.
Modern prediction algorithms, especially the ones on the P4, are accurate enough that branch penalty isn't too big a deal. The exception I can think of is very branchy software such as Office.

BTW, this entire thing came from the "deepened pipeline" phrase in the PDF that Intel released about the Prescott Instruction Set (which seems to have been yanked since).
 
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