formulav8
Diamond Member
- Sep 18, 2000
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Its no secret that K10 is a beast. According to Intels roadmaps they won't have anything changed on the core for quite awhile. So yes, AMD will be out on top when they release Barc. K10.
The K10 looks just as good to even better than Conroe on paper, plus they have the odmc and ht interconnects. If K10 doesn't outdo Conroe by 20-40% I will be dissappointed. AMD is claiming 40% more performance over Clovertown, So my expectations aren't simply far-fetched.
But only AMD knows what the true numbers are at this time. So, we will have to take their word for it till we see for ourselves.
Just my humble little opinion.
Jason
The K10 looks just as good to even better than Conroe on paper, plus they have the odmc and ht interconnects. If K10 doesn't outdo Conroe by 20-40% I will be dissappointed. AMD is claiming 40% more performance over Clovertown, So my expectations aren't simply far-fetched.
But only AMD knows what the true numbers are at this time. So, we will have to take their word for it till we see for ourselves.
Just my humble little opinion.
Jason
Originally posted by: formulav8
Its no secret that K10 is a beast. According to Intels roadmaps they won't have anything changed on the core for quite awhile. So yes, AMD will be out on top when they release Barc. K10.
The K10 looks just as good to even better than Conroe on paper, plus they have the odmc and ht interconnects. If K10 doesn't outdo Conroe by 20-40% I will be dissappointed. AMD is claiming 40% more performance over Clovertown, So my expectations aren't simply far-fetched.
But only AMD knows what the true numbers are at this time. So, we will have to take their word for it till we see for ourselves.
Just my humble little opinion.
Jason
We need to keep things in perspective here...
Barcelona vs Cloverton is a serious mismatch for Intel because C2D doesn't scale nearly as well. So the best configuration from AMD's perspective is the most cores (2P Cloverton vs 2P Barcelona). In a scenario of 8 cores, AMD's direct connect and HT should get Barcelona a 40% advantage...
However, we probably won't see that in a 1P dual core or quad core scenario. If K10 is as good as it appears on paper, then single socket "Stars" chips at the same clockspeed should be 5-10% faster than C2D...but we still don't have ANY clue as to the headroom of K10.
This will be a second generation 65nm chip with a new architecture and new thermal management and processes, so we have yet to see what it can do. We DO know that C2D has a LOT of headroom and will have more next year with Penryn, so we could see C2D released at 2 speed grades higher than K10...or not. It's also quite possible (don't choke, keep chewing) that K10 will have MORE headroom than C2D.
The bottom line is that we have absolutely no clue on speed grade matchups at this point, and current chips don't give us a hint either.
Well, one of the more respected members of Xtremesystems.org is claiming that he has access to a K10 and it's roughly 10% faster than C2D at the same clock. that 10% number seems to be pretty realistic and plausible. Of course, the real question is how high each chip can clock. It's a tough call. AMD has better power management and SOI, but being a new core it's hard to judge how well it will scale. AMD will definitely have designed K10 to scale higher than K8 (although the first chips could easily end up slower), and that's just a given. Meanwhile Intel will have 45nm and high-k. My guess is that K10 scales better than Conroe, but I'm not even going to fathom a guess how well Penryn will scale.
As for greater than 1P, it will probably take (at least) until CSI for Intel to catch up to Barcelona.
I think it's a pretty safe argument that if AMD launches against Intel's current line up that they will take the overall performance crown. The million dollar question is how long they can hold onto it.
lopri
Elite Member
- Jul 27, 2002
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Actually that claim just calls for more questions, though.
1. How does that '40% faster' is assessed? We know that these are quad-cores. If they're talking about 40% in highly multi-threaded applications, it might just well be 10% in single-threaded applications. (think games vs Cinebench)
2. What about integer performance? Why is floating point selectively commented? IIRC, AMD is launching their server-line K10 first (Barcelona), and if anything, the strong floating point performance will benefit workstations more than servers.
I'm anxiously waiting for K10 but at the same time trying not to set the expectation too high.
1. How does that '40% faster' is assessed? We know that these are quad-cores. If they're talking about 40% in highly multi-threaded applications, it might just well be 10% in single-threaded applications. (think games vs Cinebench)
2. What about integer performance? Why is floating point selectively commented? IIRC, AMD is launching their server-line K10 first (Barcelona), and if anything, the strong floating point performance will benefit workstations more than servers.
I'm anxiously waiting for K10 but at the same time trying not to set the expectation too high.
The reason for AMD's big advantage in scaling (when you add more cores to the mix) is HT and Direct Connect (the so-called "native" quad core). There is an apparent critical mass where the FSB disadvantage really comes into play...and this seems to be at >4 cores.
For instance, even on the current K8 architecture, a 1P (QC) Cloverton will slightly outdo a 2P DC Opteron at the same clock, but a 2P Cloverton can't keep up with a 4P DC Opteron (note that both have the same # of cores).
Of course, even current K8s are at least equal to Intel on FP...and Barcelona will be MUCH better on FP so it won't be close. But AMD's "claim" is that the Barcelona will be 40% faster overall than Cloverton, and I think that they aren't being selective in the benches...just the configuration (2P vs 2P). Since 8 cores of K8 is already faster than 8 cores of Cloverton, a 40% advantage makes sense.
The numbers that Hurley mentioned sound exactly right to me on a <8 core setup at the same clock...10% is about what I've been expecting.
As to scaling on Penryn, it should be about the same as C2D...there's nothing in Penryn that will improve scaling (though Bearlake might help a small bit).
I agree that Nehalem will be the next big breakout for Intel...end of 08!
lopri
Elite Member
- Jul 27, 2002
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I doubt that at this point the advantage in scaling will matter much. The scaling was big when there was one core per one socket. Now that we're heading to quad, octa cores. Ever since AMD switched to 'direct connect' architecture, practically the only way to improve performance has been clockspeeds. Probably due in part to the way architecture was built around scaling, K8 hasn't seen much benefit from bigger caches. What does that mean? That means even though the node changes and manufacturing process improves, only thing that mattered to AMD was clockspeeds. It's a stark contrast to current Core 2 Duo design which gets enormous boost from added cache. In other words when Intel goes to 45nm, they get 2 'free' boosts - clockspeed boost and additional die space for even more cache due to shrink.
This is why I am looking closely to K10's cache architecture. And there definitely is a sign that they're working on something different. Unless AMD plans to bring out a brand new architecture every other year, K10 should take advantage of larger cache. Intel is all ready'd up to shove more cache up their Core 2 design thanks to their early 45nm manufacturing. (not to mention higher clocks)
This is why I am looking closely to K10's cache architecture. And there definitely is a sign that they're working on something different. Unless AMD plans to bring out a brand new architecture every other year, K10 should take advantage of larger cache. Intel is all ready'd up to shove more cache up their Core 2 design thanks to their early 45nm manufacturing. (not to mention higher clocks)
- Oct 9, 1999
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Didn't the intial Athlon come from that company called "NextGen" or something like that?
Besides the Athlon line AMD has really never had better performing parts than Intel. AMD has always been a step behind. I don't think they seized the moment when they had it and now Intel is looming over them again.
I just don't think AMD has the technology, people, and fabs to bring ground breaking designs to market as FAST as Intel. Not that they can't do it, just not as fast as Intel and speed is the name of the game in this business.
When is K10 due? This year? Next year? It's not like Intel is standing still.
Don't get me wrong I hope AMD comes out with an ass kicking processor and sends Intel back to the drawing board. I just think it's a longshot. Intel made a wrong turn with Netburst and that really saved AMD. I don't think Intel will underestimate them again.
Besides the Athlon line AMD has really never had better performing parts than Intel. AMD has always been a step behind. I don't think they seized the moment when they had it and now Intel is looming over them again.
I just don't think AMD has the technology, people, and fabs to bring ground breaking designs to market as FAST as Intel. Not that they can't do it, just not as fast as Intel and speed is the name of the game in this business.
When is K10 due? This year? Next year? It's not like Intel is standing still.
Don't get me wrong I hope AMD comes out with an ass kicking processor and sends Intel back to the drawing board. I just think it's a longshot. Intel made a wrong turn with Netburst and that really saved AMD. I don't think Intel will underestimate them again.
Actually, scaling is just as important with the larger cores...
Remember that all of those cores have to access main memory as well as cache coherency. It's just a bit more complex now as scaling not only occurs from sockets, but on the die as well...
However scaling is much less important for the DC and QC 1P systems. As I said, there's a critical mass (which may change where it is as architectures change).
The big advantage of a large cache is that it allows a good prefetch to negate the penalties of high memory latency. That's why we don't see much gain from larger caches on Opteron, but we do on C2D...the on-die mem controller reduces those latencies significantly already.
For K8, what was more important than clockspeed was latency, latency, latency!
Do you remember the big jump in performance when Venice was released? That was because of the memory controller improvements (and their reduced latency).
I do think we will see some additional improvement from the new L3, but only because of the new prefetch on K10. Also, clockspeed should become more important on K10 because of the wider pipes...
secretanchitman
Diamond Member
- Apr 11, 2001
- 9,352
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lets hope amd can get the 65nm processors a bit better. apparently, they arent so much of a different from their 90nm counterparts.
i still say intel will be on top.
i still say intel will be on top.
NexGen were responsible for the K6 and somewhat for HT...not the Athlon.
The reason they didn't "seize the moment" is what they are suing Intel for...it's their contention that Intel illegally payed and threatened companies not to support AMD. The Japanese courts agree, now it remains to be seen if the US and EU courts do as well...
Actually, AMD has always ramped faster than Intel...but Intel has several decades and over $10 Billion lead on AMD for process technology. Most people don't realize how LOOOOOOOONG it takes for these processes to be developed (much longer than the chips themselves). Intel started work on HK+MG in the late 1990s! IBM and AMD produced the first Carbon Nanotube gate in 2001, but it probably won't be in production until 2010 at the earliest (possibly 2014).
AMD's big speed advantage is in their APM 3.0 system...Intel currently have nothing like it, and it's taken a decade to develop.
Next quarter...within the next 4 months.
And Intel is not standing still. They will have Nehalem at the end of 2008 (according to their roadmap).
Keep in mind that those drawing boards take 5 years at least. The plans for the next 3 years are already made by both companies...
True, but then neither was Pressler...I think the Brisbane would have been much better if AMD hadn't changed their cache to accomodate the new K10 chips.
- Oct 9, 1999
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So Intel knew in 2001 that Netburst would poop out in 2006 and they'd need C2D then? It seemed like C2D came out of nowhere. I don't remember hearing anything about it up until about a year before launch, maybe 18 months.
I didn't know K10 was due so soon.
Maybe I should have added "for better or for worse...".
Intel didn't know how Netburst would develop, just that the die was cast.
It takes ~5 years to go from initial concept to chip. That is why both Intel and AMD run parallel projects to see how things will develop. After the first year or 2, the project that seems best is given the green light and the others are usually shelved.
A case in point was Yamhill...it was shelved when the decision for Netburst was made.
Yamhill was actually the precursor to C2D.
As to hearing about C2D, the facts aren't usually made public until 2 or 3 years before release, but Core and Core 2 were a special case. First, it was a pickup from the Yamhill project. Second, Intel cancelled numerous projects (e.g. Whitefield) to rush Core along as fast as they could by reassigning teams to all work on Core.
So you're right that Core was a once-off (and a very expensive one at that!).
The founder of AMD (Jerry Sanders III) had a great quote that described the process...
"The semiconductor industry is like a wierd form of Russian Roullette. You pull the trigger and 3 years later you find out if you blew your brains out"
Originally posted by: Viditor
Maybe I should have added "for better or for worse...".
Intel didn't know how Netburst would develop, just that the die was cast.
It takes ~5 years to go from initial concept to chip. That is why both Intel and AMD run parallel projects to see how things will develop. After the first year or 2, the project that seems best is given the green light and the others are usually shelved.
A case in point was Yamhill...it was shelved when the decision for Netburst was made.
Yamhill was actually the precursor to C2D.
As to hearing about C2D, the facts aren't usually made public until 2 or 3 years before release, but Core and Core 2 were a special case. First, it was a pickup from the Yamhill project. Second, Intel cancelled numerous projects (e.g. Whitefield) to rush Core along as fast as they could by reassigning teams to all work on Core.
So you're right that Core was a once-off (and a very expensive one at that!).
The founder of AMD (Jerry Sanders III) had a great quote that described the process...
"The semiconductor industry is like a wierd form of Russian Roullette. You pull the trigger and 3 years later you find out if you blew your brains out"
I thought Yamhill was the 64bit variant of netburst cores at the time. Could have swore reading about it forever and ever at the INQ.
It was 64bit, but it wasn't Netburst (in fact it was the opposite philosophy...more like the K7 core with a high IPC rather than a high clock).
It was dropped by management for 3 major reasons:
1. Intel had signed a development deal with Rambus, and RDRAM was a much better match with the Netburst architecture than it was with the high IPC Yamhill (or Hammer). This would have given Intel both a financial and tech edge on AMD if they could have pulled it off...
2. Those days were the height of the "Mhz Myth", and marketing for a high clockspeed was far easier and more effective than high IPC.
3. Intel was already developing high-k/metal gates, and they were too optimistic about when they would be able to solve the leakage problem. Initially, Intel expected Netburst to eventually hit 10GHz...ooops.
Not trying to disagree with you, my memory is fuzzy, but a quick google of "Yamhill Intel" turned up this wiki link regarding Intel's 64bit implementation in Prescott:
EM64T/Yamhill/Prescot
Does this jive with your recollection? Wiki != Correct all the time, so I understand if you find it to be in error.
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