Poll: SiS730S S2K Design Problem

[cpuhunter5]

I have come across an issue regarding SiS730S S2K design,

and I am wondering if there are people who have the same

concern an mine.



According to AMD athlon System Bus Design Guide's recommendation,

to ensure optimal current return path, S2K Pad rings need to include

decoupling from VccCore to Vss, i.e. each S2K signal must be adjacent

to a VTERM (CPU Core Power) signal or a GND (Ground) signal in the

S2K quadrant.



Figure shown (as attached) is indicating that SiS730S is not following

such recommendation, which could cause poor signal quality.



I am worrying that this issue will generate bigger problem due to

instability of signaling, especially if the CPU signal sent to SiS730S

is also unstable (either too strong or too fast).



Under system tests, system uses SiS730S might encounter system

crashes especially when is tested under different CPU host frequencies

and clock ratio.



I am not sure is there anyone has already encountered this issue,

or might have the same concern as me. Please help.


🙁

 

[Peter]

What do SiS technical support team say? They would be the first I'd ask.

(I'd be surprised if you'd find more than a couple of engineers involved in mainboard design in this forum ...)

Regards, Peter

 

[Peter]

hm.... having seen your post on other boards too, no offense intended, I can't resist asking whether you actually are a concerned design engineer.

Or is that just a FUD campaign against the SiS/AMD combination? (Point being that actual product using SiS 730S are already appearing on board manufacturers' websites ...)

Regards, Peter