Some interesting information has been released at the latest Platform Conference. Here is an excerpt:
<< Dispelling recent rumors, AMD confirmed that SSE2 will be included in all Hammer processors, including the Clawhammer, which is scheduled to debut later this year. The Hammer line will be the world's first 64-bit enabled x86 microchips. Not only will Hammers be fast, but the move to 64-bits will allow the chips to work in much larger servers demanding vast memory arrays.
Although not providing explicit conformation, responding to another VHJ question, AMD divulged additional information on its direction towards multi-core designs (a multi-core chip has more than one CPU on a die). The embedded Hammer North Bridge has two CPU interfaces. As AMD's process technologies move to smaller geometries, multi-core will become increasingly attractive and, thanks to the Hammer North Bridge design, easily achievable. >>
Check out the rest of it right here.
<< Dispelling recent rumors, AMD confirmed that SSE2 will be included in all Hammer processors, including the Clawhammer, which is scheduled to debut later this year. The Hammer line will be the world's first 64-bit enabled x86 microchips. Not only will Hammers be fast, but the move to 64-bits will allow the chips to work in much larger servers demanding vast memory arrays.
Although not providing explicit conformation, responding to another VHJ question, AMD divulged additional information on its direction towards multi-core designs (a multi-core chip has more than one CPU on a die). The embedded Hammer North Bridge has two CPU interfaces. As AMD's process technologies move to smaller geometries, multi-core will become increasingly attractive and, thanks to the Hammer North Bridge design, easily achievable. >>
Check out the rest of it right here.
