Phenom: Effect of Memory Controller clock speed?

[toslat]

How much improvement would Phenom see if they got the memory controller clock upto speed or exceed the core clock?
Also add into the mix the use of lower latency RAM.

 

[Toadster]

Originally posted by: toslat
How much improvement would Phenom see if they got the memory controller clock upto speed or exceed the core clock?
Also add into the mix the use of lower latency RAM.

i'm only commenting on your signature...

I've heard it as

"I had the blues because I had no shoes,
until upon the street - I met a man who had no feet"

 

[myocardia]

You're misinformed. It's only the L3 cache that they are having to run slower than the core clock. And my best guess would be that it would probably add ~5% performance, though probably less in some instances, and possibly more in others.

 

[gOJDO]

@myocardia
It is the L3 and the NB running slower than the cores.

@toslat If you want to know how K10 will perfrorm with a faster RAM: going from DDR2-800 do DDR2-1066 brings 0 to 5% performance improvement. Going from DDR2-1066 CL5 to CL4 brings less than 1%. Not enough to salvage Phenom. If they can boost the L3 and the NB frequency up to the cores frequency, that might result to another 0-5%. Thats less likely to happen.

 

[myocardia]

Originally posted by: gOJDO
@myocardia
It is the L3 and the NB running slower than the cores.

Well of course the HT bus is running slower. You didn't think they were going to make it 25 times faster, from one generation to the next, did you?

 

[gOJDO]

The NB and the HT are completely different things. The NB is a kind of a router, while the HT is a bi-directional point to point bus. The NB(northbridge) is conneced to the L2 of all 4 cores, to the L3, to the memory controllers and to the HT bus(es). Its frequency is not equal to the HT bus frequency, but these two frequencies are somehow related. The HT bus speed depends of the NB speed.

Since you mentioned the previous generation, there is a huge difference between the NB of K8 and K10. K10 NB size is more than twice the size of K8 NB. It not only connects more resources then the NB of K8, but it is much more advanced, thus it has a much complex logic design. At first AMD planned the NB and the L3 to clock higher then the cores, but due to the complexity of the NB and the L3 they were forced to clock them slower then the cores. The low L3 & NB frequency hurts the performance of K10 in both single-threaded and multi-threaded software and diminishes the point of the so called "native" quad-core.

 

[Keysplayr]

The Pentium 4 was a VERY complex design when it came out as well. Substantially more complex than the Pentium III it was meant to replace. I sincerely hope this is not AMD's version of the P4. An extremely complicated architecture could, well, complicate things. LOL.

 

[Zoomer]

A quicker L3 cache would only help performance, since it would reduce wait times for a L3 cache hit. I think it should be important; why else would they go to the trouble of doing so?

Unless they are running out of ideas, in which case I would suggest a thorough examination of the core chips under suitable equipment.