pentium 4 and bandwidth

[sonoma1993]

What makes the pentium 4 so bandwidth hungry? is it due to the high clockspeed? the 30+ some pipelines? or what?

yeah im refering to the memory bandwidth. Im also assuming the penitum 4 is also hungry for fsb bandwidth too.

 

[redhatlinux]

I'm not sure that the 30+ pipelines is actuall correct. I assume that you are referring to memory bandwidth. The reason that they are 'so hungry' is two fold. 1. The caching architecture on the P4 is very different, and really not very good IMHO. The high clock speed, does infact contribute to the thirst for memory. I am not sure what the cache hit rate would be on a P4 running some of the heavy benchmark loads that we see used in this forum, but my guess is that it would NOT be as high as say the equivalent AMD cpu. The X86 design has so few General Purpose Registers that almost all instructions require the use of main Memory. Memory access is very slow compared to the speed of the processor, good caching algorithms drastically reduce the wait time in the cpu pipeline for data to perform calculations. Consider the CPU to be a large fire, the more wood that you provide it, the more heat it produces.

 

[BitByBit]

The P4 isn't necessarily as bandwidth hungry as people think.
The move to a 1066MHz FSB gave the P4 a negligable boost at best, which suggests that an 800MHs FSB can supply most of the bandwidth the P4 at its current speeds can use.

The impact of memory bandwidth is really dependent on the type of application running.
'Streaming' applications, such as encoding and compression tend to have low temporal and spatial locality, which means its data is very difficult to cache. In this case, memory bandwidth can become a bottleneck if the memory isn't able to supply the processor with data rapidly enough.
The rate at which a processor running these types of applications uses up memory bandwidth is more dependent on the processor's throughput than clock speed, although these applications tend to have low ILP and thus tend to do better on the P4, due to its higher clock speeds.
This may be why the P4 has earned a reputation of being 'bandwidth hungry'; the very applications which the P4 excels at are the ones that prefer memory bandwidth over cache.

The P4 'Prescott' has 31 pipeline stages. This has little to do with the impact memory bandwidth has on performance, since the maximum throughput a processor can achieve is dependent on its execution core width and clock speed.

Theoretical Maximum Performance (instructions / sec) = IPC[max] X Frequency.