PCI-Express Physical Layer?

[Mephala]

Does anybody know what kind of SerDes the new PCI-Express interfaces will be running on? Everybody's all obsessed with the new spec but if it's on some budget Mux/Demux I'd be kind of apprehensive. As far as I know (and I don't know much about AGP), AGP is just a bus so it matters less, but for a point-to-point link one wonders. Particularly the serdes components could be a huge bottleneck IMO. Or is the serdes totally determined by the cards as distinct from the northbridge? My sifting has failed to turn much up; it would be nice if someone more well-versed in this stuff would help me out.

Also, if the serdes is totally determined by the ATI--er--external card--, would there be a market in bridge technology to other interfaces (parallel buses like Redwood, or even Serial RapidIO)?

 

[AndyHui]

Have you read this thing that I wrote? Not sure if it answers your question though, as I am not entirely understanding what you are asking.

My article also answers your other question in regard to PCI Express being used as an FSB.

 

[Mephala]

Thank you very much for that article; it was very helpful, but on the other hand it did not answer my question, which depending on whether I quite get it or not may not be pertinent; but PCI-Express is a serial interface, right? So what implementation of the serdes units will be put in place at the PHY level, i.e. RaSer?