PCI-e slot Bandwidth

[hennessy1]

Probably easy but stupid question. Is there any motherboard out there that can run all its x16 slots at full bandwidth regaurdless of how many other x16 slots on the board are occupied? (e.g. 3 or more x16 slot boards.)

 

[lopri]

You should look at the number of PCIe lanes provided by a given chipset, instead of the slots on a motherboard. For example,

X58: 36 lanes (plus 8 Gen 1 lanes from ICH10R)
P55: 16 lanes (plus 10 Gen 1 lanes from PCH)
790FX: 42 lanes
790X: 22 lanes

A board can add additional switches (NF200..) and all that, but the aggregate bandwidth is limited by the chipset itself.

 

[heyheybooboo]

The MSI 890FX-GD70 might have something to offer.

You just have to wait until April/May to find out - LOL



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[hennessy1]

This was more of an expeditionary question then a problem with my current hardware. I just see lots of posts about if you use this x16 slot then this bumps down to 8x and so on. I just didn't know if there was a board that can run all those slots populated in a full x16 bandwidth.

I also assume with these higher power cards from both ati and nvidia coming that there will be a need to have full bandwidth in that GPU slot regardless if there is other x16 slots populated by add-in cards.

 

[Fox5]

I think some of the high end nforce boards could do 3 slots at 16x.

 

[Fox5]

This was more of an expeditionary question then a problem with my current hardware. I just see lots of posts about if you use this x16 slot then this bumps down to 8x and so on. I just didn't know if there was a board that can run all those slots populated in a full x16 bandwidth.

I also assume with these higher power cards from both ati and nvidia coming that there will be a need to have full bandwidth in that GPU slot regardless if there is other x16 slots populated by add-in cards.

Video cards use external power connectors so they don't need the full power provided by a pci-e slot. They probably use barely any of it.

 

[lopri]

@heyheybooboo: your link is broken. Got better pics from here.

file:///C:/Users/Kane/Downloads/eureqa_intro_wmv.wmvhttp://www.coolaler.com/showthread.php?t=225951

Looks definitely sexy, but I wonder if these will support Bulldozer, or even that's a good idea. AMD should move on to LGA sockets with Bulldozer. ZIF sockets had their time and it's now so labrorious to swap AMD CPUs. I thought AMD would move to LGA socket with Bulldozer?

 

[ekoostik]

P55: 16 lanes (plus 10 Gen 1 lanes from PCH)

The P55 has 8 available lanes from the PCH. There is a 9th used by the LAN controller. I checked out the spec, there may be a 10th used by the High Definition Audio Interface so maybe there are 10 total. But only 8 available.

Block diagram: http://www.anandtech.com/weblog/showpost.aspx?i=641
Datasheet I reviewed (.pdf), pp. 37-38: http://www.intel.com/Assets/PDF/datasheet/322169.pdf

 

[hennessy1]

I didn't mean x16 from an electrical standard. I meant it from a signaling or bandwidth standard. I apologize if those are the same thing and I am just mixing them up.

 

[heyheybooboo]

@heyheybooboo: your link is broken. Got better pics from here.

file:///C:/Users/Kane/Downloads/eureqa_intro_wmv.wmvhttp://www.coolaler.com/showthread.php?t=225951

Looks definitely sexy, but I wonder if these will support Bulldozer, or even that's a good idea. AMD should move on to LGA sockets with Bulldozer. ZIF sockets had their time and it's now so labrorious to swap AMD CPUs. I thought AMD would move to LGA socket with Bulldozer?

I gots no links and can't back this up but here goes ...

G34 on the enterprise side will be fully land grid. IIRC there will be a gazillion (highly technical term) pins because of a re-design of the IMC and a doubling (?) of the HT links for inter-CPU communication on 4p/8p. This is a big step forward for the NUMA arch because of the latency inherent with CPU0 communicating with the DIMM bank of CPU3, for example. It is Page Fault City when CPU0 looks first to its own DIMM bank ... and then must look elsewhere at another DIMM bank. It is the NUMA Hell that you never hear about with 2P/4P/8P.

'Bulldozer' (like 'Westmere') is a class of processors. My impression from what info is floating around is that the first chips will be AM3 backward compatible and will work in what I believe is called AM3r2 (which will most likely end up being called AM3+). Still zif

The first Bulldozer is 'Zampezi' (probably not very close - LOL) and will be AM3+. The rumahs seem to believe it will be backward-compatible with AM3 but may lose some advanced HT3 tech from AM3+.

Following that, the land grid 'new socket' will most likely arrive with the Bulldozer Fusion microprocessor, with the GPU integrated on die --- I think that is called Lano.

You will be tested later

I had thought the 890 series was going to launch PCIe Gen3 but maybe that will go with the AM3+. PCI-SIG seems to be kicking Gen3 down the road a bit. Need more jigawatts to the PCIe slot, Captain? - LOL


I found this over at XS

No socket defined for 'Llano'. I imagine that's the end of zif for AMD.


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