PCI-e 5.0 (128GB/s) coming in 2019. Running a 32GHz....

[William Gaatjes]

This is an interesting article about upcoming pci-e 4.0 and 5.0.
It explains how the bottle necks start to arise again in (server) systems.
It will be a while though before we will see it in consumer space.
I wonder if we ever will see it. Might demand special pcb material.

https://www.nextplatform.com/2017/07/14/system-bottleneck-shifts-pci-express/

 

[Topweasel]

This is an interesting article about upcoming pci-e 4.0 and 5.0.
It explains how the bottle necks start to arise again in (server) systems.
It will be a while though before we will see it in consumer space.
I wonder if we ever will see it. Might demand special pcb material.

https://www.nextplatform.com/2017/07/14/system-bottleneck-shifts-pci-express/

Looks like it's nearing time for a new standard connector type. Maybe one with some DDR or QDR features built in to overcome requiring insane clocks.

 

[scannall]

This is an interesting article about upcoming pci-e 4.0 and 5.0.
It explains how the bottle necks start to arise again in (server) systems.
It will be a while though before we will see it in consumer space.
I wonder if we ever will see it. Might demand special pcb material.

https://www.nextplatform.com/2017/07/14/system-bottleneck-shifts-pci-express/

From other articles I've read, the consumer space will likely skip pcie4 and go straight to 5. IBM uses 4 currently in some of their systems. It should make the 2020 offerings interesting.

 

[cbn]

From other articles I've read, the consumer space will likely skip pcie4 and go straight to 5.

That is what I have read also:

http://www.networkworld.com/article...ress-4-0-is-done-5-0-spec-nears-approval.html

PCI Express 3.0, or PCIe, was finished in 2010, and motherboards began to appear in 2011. The 4.0 spec should have been done within three years but only now is being finished because if there’s one way to screw up development, it’s to have it done by committee, and 700 cooks can really spoil the broth.

Now the PCI-SIG has announced that PCIe 4.0 specification is finished, and it plans to have PCIe 5.0 ready to go by 2019, which is liable to cripple the 4.0 spec before it even gets out of the gate.

 

[William Gaatjes]

Amazing that they can reach those speeds. CWDM (Coarse Wavelength Division Multiplexing) is an optical solution, i wonder how long it will take for optical connections replace copper traces.
https://en.wikipedia.org/wiki/Wavelength-division_multiplexing
The board layout designer must be really using all analyze tools available to meet the stringent requirements.

 

[Carfax83]

Looks like PCI-e 5.0 will surpass even RAM bandwidth on mainstream CPUs with dual channel. I've been waiting for an announcement on PCI-e 4.0, as I promised myself I wouldn't update my rig until PCI-e capable motherboards and CPUs become available. What's the chances that Intel will release PCI-e 4.0 capable motherboards and CPUs next year?

 

[NostaSeronx]

PCIe 5.0 looks child-ish to IFX(Infinity Fabric eXpansion)((512 GB/s(No SerDes) bi-der max) and NVLink X(<800 GB/s(SerDes) bi-der max).

 

[whm1974]

OK how much will this cost? I for one can imagine that the consumer space will not see this tech for years yet.

 

[William Gaatjes]

I needed a short refresh course.
For those interested :
http://www.hardwaresecrets.com/everything-you-need-to-know-about-the-pci-express/