Would you mind providing more info on Tcase. I saw the link and it stated 72.6. When using RealTemp and running IBT, if the temps are spiking from 70's to low 80's, what impact does that have on the chip? Are we running it well past spec at that point?
TJmax is set to protect your cores, and it is 98C. Tcase is set to protect the socket and the surrounding electronics.
There is a thermal gradient that exists between the point where the heat is generated (the xtrs and the wires) and the physical location where Tcase is spec'ed.
Because the DTS are located closer to the source of the heat generation than the Tcase location, we expect the DTS temp to be a more accurate representation of the temperature experienced by the CPU IC itself, which is also why the TJmax value is higher (98C) than Tcase (72.6C).
We can't
easily measure Tcase, it requires milling a divet in the surface of the IHS and placing a thermocouple there, sandwiched between the IHS and the HSF.
But we can use our knowledge of the
heat equation to rationalize that the Tcase temp will always be less than the DTS temp, and if the DTS temp is anywhere close to the TCase max spec then we are reasonably assured the actual Tcase temp is below the spec limit for max Tcase temp.
Your chip can spike in temps all the way up to TJmax and still be fine, that is why TJmax is TJmax. If it wasn't ok to hit TJmax then Intel would have set TJmax to a lower temp to begin with.
What you don't want to do is hit TJmax while
appreciably over-volting...unfortunately without a Vmax spec we really have no basis for establishing a working Vmax.
Arrhenius equation guides us to roughly expect the chip's lifetime to double for every 10C we can reduce its operating temps. The chip will have been engineered to have a certain intrinsic lifetime if operated at TJmax provided the thermal gradient is such that the TCase max is honored.
Operating 88C instead of 98C will double the chip's expected lifetime. 78C will double it yet again. 68C yet another doubling.
But raising voltage has the opposite effect. Raising voltage reduces lifetime expectations in the same sort of logarithmic effect (voltage lowers the activation barrier, kind of like a catalyst).
So raising your voltage ~3% will reduce the chip lifetime by a factor of ~2x.
If your chip is supposed to last 10yrs if subjected to near-98C operating temps at 1.35Vcc but you take it down to ~68C operating temps (expected lifetime becomes 40yrs) but you raise the voltage to 1.44V (~6% over the stock volts) then your lifetime is back to being an expected 10yrs.
However, if you are running 1.44V and your operating temps are more like 78C than 68C then your expected lifetime would be only 5yrs...and if your temps end up being in the 80's at that voltage then you can expect your chip to last maybe 2-3 yrs.
Also on the OC front, if I gather what you're saying, to obtain OC on SandyBridge K series, you should:
Enable PLL
Reduce Load Line Calibration from max (where it fluctuates voltage the most) to medium
Manual set the voltage offset
On the manual volate offset. If the goal is to get a stable OC at 1.35v, I'd set the offset to be +0.1v since the base voltage is 1.25v?
Yes.
If the offset allows for 1.35v, won't having PLL enabled bump the vcore up as needed during the testing phase?
That's not what the "PLL overclock enabled" means or does. It is the phase-loop-lock circuits used by the circuits in the system agent to do its job, apparently these circuits limit the overclockability of the core logic circuits unless the mobo is allowed to overclock them transparently to us users. The downside is, reportedly, that your desktop rig might not wake up if it goes to sleep, required a hard-boot.
Solution to that is to not set your power-plan to allow the rig to go to sleep. Have it either idle or hibernate, just no sleeping.
Finally, my temps on the 212+ can shows upto an 8c diff between the cores. Should I reset the heatsink and reapply the thermal compound? I'm using MX-4 so I dont' think the compound is the issue.
It's unavoidable owing to the
asymmetry of the sandy bridge chip itself. The thermal diffusion mechanics pretty much make it an unavoidable reality.
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