Mark Papermaster interview by Ian Cutress:
https://www.anandtech.com/show/1617...ermaster?utm_source=twitter&utm_medium=social
This is a nice point, Ian also touched upon in his youtube channel (
tech-tech potato):
So Zen 3 is the ground-up redesign Jim Keller mentioned. That should mean there are again low-hanging fruit to pick for Zen 4.
My favorite points:
1) "It is in fact the core is in the same 7nm node, meaning that the process design kit [the PDK] is the same. So if you look at the transistors, they have the same design guidelines from the fab."
2) "as you look at the implementation and literally across all of our execution units, Zen 3 is not a derivative design"
3) "It was tremendous engineering on the reorganization on the Zen 3 core that truly delivers the benefit in reduced latency"
4) "when you add the amount of logic changes that we did to achieve that 19% IPC, normally of course the power envelope would go up. [...] So I think your readers would have naturally assumed therefore we went up significantly in power but the team did a phenomenal job of managing not just the new core complex but across every aspect of implementation and kept Zen 3 in the power envelope that we had been in Zen 2."
5) "The load/store enhancements were extensive, and it is highly impactful in its role it plays in delivering the 19% IPC. It’s really about the throughput that we can bring into our execution units. So when we widen our execution units and we widen the issue rate into our execution units it is one of the key levers that we can bring to bear. So what you’ll see as we roll out details that we have increased our throughput on both loads per cycle and stores per cycle, and again we’ll be having more details coming shortly."
- They achieved a 19% IPC and 24% performance per watt gain without any significant process change.
- He states that it's logic changes that achieved the 19% IPC uplift and goes on to detail wider execution units, load-store changes, and so on. When he describes the 19% IPC uplift and where it came from he does not credit the larger cache. I think the clear message is that this is a major core redesign that happens to also benefit from a larger L3$.
- This is also very interesting to me especially looking forward at AM5 and 5nm. Work out the kinks on a new design rather than taking on that issue PLUS a new socket and process.
Future-looking:
1) "if you look to the future we drive improvements in every generation. So you will see AMD transition to PCIe Gen 5 and that whole ecosystem. You should expect to hear from us in our next round of generational improvements across both the next-gen core that is in design as well as that next-gen IO and memory controller complex."
- Assume by "next round of generation improvements" he means Zen4, meaning it will also feature a next-gen IO and memory controller complex, and next-gen core. While he mentions PCIe 5, this sounds like more of a "we'll do it eventually" rather than giving a timeframe for it.
Slightly off-topic from Zen3 in particular, but still interesting:
1) "It’s not about ISA (instruction set architecture) - in any ISA once you set your sight on high performance you’re going to be adding transistors to be able to achieve that performance. There are some differences between one ISA and another, but that’s not fundamental - we chose x86 for our designs because of the vast software install base, the vast toolchain out there, and so it is x86 that we chose to optimize for performance. That gives us the fastest path to adoption in the industry."
- There is an extremely high level of pragmatism at play in AMD's decision-making here, refreshing to see some realism in addition to the massive advancements they're making.