but clock speed is a part of cpu arquitecture ¬¬
He's misusing the term "architecture." To him it represents IPC in general (which itself doesn't make too much sense) rather than "core design" or actual CPU architecture. I think he's confusing "core architecture" with "CPU architecture" (which is used on marketing slides as "architecture" referring to core architecture), but even then both have IPC included in their terms and their specificity would depend on the uncore, and to confuse it even further that too has a say in core architecture. He's not ignoring clock speeds but also cache, IMC, on-die GPUs, perf-per-watt, die size, transistor density, and essentially everything else that goes into CPU architecture as these all have a say in performance.
To clarify a bit, let's take AMD's Piledriver:
Piledriver is the core architecture but is featured in both Trinity and Vishera. They're essentially the same design except that Trinity is an APU and Vishera is a desktop CPU, lacking the on-die GPU, while Trinity lacks the 8MB L3 cache that Vishera has. Both are still sharing the same core architecture (or more accurately modular core design) therefore AMD refers to both as Piledriver on their slides.
IPC, though, would differ on the workload despite the same core architecture as the cache plays a major role (remember that IPC varies depending on the workload). Furthermore, Vishera is supposedly getting a couple of other goodies on top of the Trinity Piledriver module so that too may have an impact on IPC despite the fact that they still share the same core architecture.
He's got valid points that I agree with, for example Bulldozer being an architectural screwup because of the chase for clock speeds (and the other being the CMT approach which he hasn't), but he's woefully confusing his terms and assuming that it's far less complicated than it really is.
And to twist things even more, AMD initially designed Bulldozer because they knew they'd never catch Intel in IPC due to fab advantage. So even fabs have a massive impact on IPC and CPU architectures. Talk about complicated
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