Official: AMD re-introduces FX Brand for high-end Processors

[sm625]

off the top of my head if AMD really wanted to try and push Bulldozer as an enthusiast grade gaming product I'd wager they'd need to tie it to some sort of app or feature like recording/encoding gameplay video on the fly (something like FRAPS) and then editing/encoding for posting to video sharing sites.

This would be awesome. Dedicated hardware in the gpu that takes the display output and compresses it and streams it back into ram so it can be captured and placed into an avi container. I would be recording stuff all the time if it didn't carry a noticeable cost in system resources.

 

[Abwx]

Peak sustainable throughput may be the same -- but I believe the idea is that average throughput is going to be much higher.

Average throughput will be way higher in BD since there cant be 100% 256bit AVX code for FP purpose , so we can expect 50% more average throughput for BD since it will have double the peak throughput either
with regular X87/SSE code and with 128bit AVX code.

 

[Idontcare]

So it is using the revised power plane thing from the original Phenom? Or did Phenom II had that, I lost track of it.

IIRC this portion of the original CnQ of Phenom was busted (failed to function as intended in realworld scenarios, actually degraded performance and so many Phenom users just disabled CnQ...Anand had an article on this IIRC) and it was completely pitched out when they did PhII.

Maybe they redid it for BD?

 

[Tuna-Fish]

IIRC this portion of the original CnQ of Phenom was busted (failed to function as intended in realworld scenarios, actually degraded performance and so many Phenom users just disabled CnQ...Anand had an article on this IIRC) and it was completely pitched out when they did PhII

It failed because back then windows randomly tossed threads from core to core, without any regards to the power-state the cores in question were in. End result = massive performance degradation as active threads land on a dialed-down core twice a second.

I think MS finally fixed it on their end.

 

[chihlidog]

AMD's official FX website is now live:

http://sites.amd.com/us/promo/processors/Pages/fx-processor.aspx

 

[SlowSpyder]

Maybe my memory is just hazy, but it seems to me that AMD is less shy in regards to talking about Bulldozer before it hits the market than with they were with Phenom. Hopefully that's a good sign.

 

[chihlidog]

Can anyone watch the video and post a summary? I am at work so I cant watch it.

 

[formulav8]

IIRC this portion of the original CnQ of Phenom was busted (failed to function as intended in realworld scenarios, actually degraded performance and so many Phenom users just disabled CnQ...Anand had an article on this IIRC) and it was completely pitched out when they did PhII.

Maybe they redid it for BD?

Edit: Someone already mentioned what I said.

There was nothing wrong with the Ph1's approach. It was mainly Windows scheduling in Vista that was the main portion of the problems.

 

[chihlidog]

No summary of the vid?

 

[busydude]

No summary of the vid?

Nothing much going on there.. bunch of marketing crap. Worlds first unlocked 8-core CPU... combine it with worlds fastest graphics card(6990) and all that you know is about to change. also.. some footage from DiRT 3 and Deus EX.

 

[Skurge]

Nothing much going on there.. bunch of marketing crap. Worlds first unlocked 8-core CPU... combine it with worlds fastest graphics card(6990) and all that you know is about to change. also.. some footage from DiRT 3 and Deus EX.

Don't forget the gravely voice.

 

[Skurge]

http://www.youtube.com/watch?v=Jn2qcOweRYY

Well at least we know it works.

 

[PlasmaBomb]

Is it better now?

Sure I love having multipliers at x2.5, x4.5, x5, x6, x7.5, x8.5, x10 when the CPU is idle...

Much like I love my chips idling at 1.40V...

 

[PlasmaBomb]

well theres Truecypt 7.0,dont know why they let this slip?

Doesn't implementing AES give it a massive boost anyway?

In which case it isn't that impressive...

 

[drizek]

It's actually pretty terrible if that is all they get from AES-NI, although they don't show the actual numbers, just say it is >2x.

The Xeon W3680 gets 4.7GB/s. AMD is saying that they only get >1.6GB/s, which is a long way away from what Intel is doing, not that it actually matters in practice though. The important thing is that it doesn't use up CPU power. My Phenom II X3 runs at 100% and maxes out at 400MB/s, which is pretty bad with modern SSDs.

 

[busydude]

It's actually pretty terrible if that is all they get from AES-NI, although they don't show the actual numbers, just say it is >2x.

It says.. 797 for 1100T and >1600 for AMD FX.

 

[drizek]

It says.. 797 for 1100T and >1600 for AMD FX.

I had edited my post.

Again, >1600 could mean anything.

 

[Khato]

Sure I love having multipliers at x2.5, x4.5, x5, x6, x7.5, x8.5, x10 when the CPU is idle...

Much like I love my chips idling at 1.40V...

I'm actually kinda hoping that these are nothing more than further glitches with the software. Why? Because if it is correct, then integer core frequency is not dependent upon module frequency... Which leaves us with no indication whatsoever of the frequency(or possibly frequencies) of other module logic. Best case is that the other logic would have separate multiplier control that's user accessible... worst case is that they're running at slower frequencies with no method other than base clock increase for overclocking... or that they're simply incapable of running at higher frequencies and hence are treated like the 'uncore' in Intel's Nehalem.

Interesting sidenote here being that according to block diagrams, AMD's integer core consists of the same functional blocks as the double-clocked ALU's on the Pentium 4, which was, I believe, the last consumer processor design to have different clock frequencies on core logic. At least Intel's marketing refrained from calling the 1.5GHz Williamette a 3GHz processor just because that's what the integer logic ran at.

 

[PlasmaBomb]

I had edited my post.

Again, >1600 could mean anything.

Yup... it could mean 1601 or it could mean >2000 or more, but you would think that if they could hit over 2400 (x3) they would have gone with ">x3 Improvement!!"

 

[Arzachel]

idle

What makes almost every one of you think that the chip is idle? The graphs indicate all the cores are under load though small it might be. Don't intel CPU's turbo even at small loads to make the task finish faster? And isn't the frequency so low on a few cores, because they are the least loaded and it comes in small bursts, so the frequency shown is (max freq+idle freq)/time?

 

[Plimogz]

Sure I love having multipliers at x2.5, x4.5, x5, x6, x7.5, x8.5, x10 when the CPU is idle...

Much like I love my chips idling at 1.40V...

You're ignoring the two cores which have dropped down to 1.0625V. Good to see those after that earlier screen which had all eight at 1.40V.

Although I do wonder where all of the intermediate P-States are. (as seen down there)

Binaries
-------------------------------------------------------------------------

CPU-Z version 1.56.4

Processors
-------------------------------------------------------------------------

Number of processors 1
Number of threads 8

APICs
-------------------------------------------------------------------------

Processor 0
-- Core 0
-- Thread 0 0
-- Core 1
-- Thread 0 1
-- Core 2
-- Thread 0 2
-- Core 3
-- Thread 0 3
-- Core 4
-- Thread 0 4
-- Core 5
-- Thread 0 5
-- Core 6
-- Thread 0 6
-- Core 7
-- Thread 0 7

Processors Information
-------------------------------------------------------------------------

Processor 1 ID = 0
Number of cores 8 (max 8)
Number of threads 8 (max 8)
Name AMD Processor
Codename Bulldozer
Specification AMD Eng Sample, 1D26246W8K44_36/26/22_2/8 (Engineering Sample)
Package Socket AM3+ (942)
CPUID F.1.0
Extended CPUID 15.1
Core Stepping
Technology 32 nm
TDP Limit 149 Watts
Core Speed 1400.0 MHz
Multiplier x FSB 7.0 x 200.0 MHz
Instructions sets MMX (+), SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, x86-64, AMD-V, AES, AVX, XOP
L1 Data cache 8 x 16 KBytes, 4-way set associative, 64-byte line size
L1 Instruction cache 4 x 64 KBytes, 2-way set associative, 64-byte line size
L2 cache 4 x 2048 KBytes, 16-way set associative, 64-byte line size
L3 cache 8 MBytes, 64-way set associative, 64-byte line size
FID/VID Control yes
Min FID 7.0x
P-State FID 0x14 - VID 0x0B - IDD 12 (18.00x - 1.412 V)
P-State FID 0xE - VID 0x0E - IDD 10 (15.00x - 1.375 V)
P-State FID 0xA - VID 0x16 - IDD 10 (13.00x - 1.275 V)
P-State FID 0x7 - VID 0x1B - IDD 9 (11.50x - 1.212 V)
P-State FID 0x4 - VID 0x21 - IDD 8 (10.00x - 1.137 V)
P-State FID 0x1 - VID 0x26 - IDD 6 (8.50x - 1.075 V)
P-State FID 0x10C - VID 0x30 - IDD 6 (7.00x - 0.950 V)

Package Type 0x1
Model 00
String 1 0x0
String 2 0x0
Page 0x0
TDC Limit 96 Amps
Attached device PCI device at bus 0, device 24, function 0
Attached device PCI device at bus 0, device 24, function 1
Attached device PCI device at bus 0, device 24, function 2
Attached device PCI device at bus 0, device 24, function 3
Attached device PCI device at bus 0, device 24, function 4
Attached device PCI device at bus 0, device 24, function 5

 

[podspi]

What makes almost every one of you think that the chip is idle? The graphs indicate all the cores are under load though small it might be. Don't intel CPU's turbo even at small loads to make the task finish faster? And isn't the frequency so low on a few cores, because they are the least loaded and it comes in small bursts, so the frequency shown is (max freq+idle freq)/time?

Yea, I am not sure why this keeps on getting repeated. Current Intel and AMD chips both boost up to their max-sustainable (or higher) clockspeeds WELL before they reach full-utilization.


It doesn't mean that CnQ or TC 2.0 is borked, and if the screenshot indicated that it was, I doubt AMD would have let that slip out instead of some generic looking task manager thing instead.

 

[Drakula]

IIRC this portion of the original CnQ of Phenom was busted (failed to function as intended in realworld scenarios, actually degraded performance and so many Phenom users just disabled CnQ...Anand had an article on this IIRC) and it was completely pitched out when they did PhII.

Maybe they redid it for BD?

It failed because back then windows randomly tossed threads from core to core, without any regards to the power-state the cores in question were in. End result = massive performance degradation as active threads land on a dialed-down core twice a second.

I think MS finally fixed it on their end.

Edit: Someone already mentioned what I said.

There was nothing wrong with the Ph1's approach. It was mainly Windows scheduling in Vista that was the main portion of the problems.

Sweet, thanks for answering my question about the Cool n' Quiet. Always liked the idea of their implementation of it for the original Phenom, and did remember there was problem about it, but forgot what the cause was. Good to see it is still alive and kicking in some form.

 

[CPUarchitect]

Average throughput will be way higher in BD since there cant be 100% 256bit AVX code for FP purpose , so we can expect 50% more average throughput for BD since it will have double the peak throughput either with regular X87/SSE code and with 128bit AVX code.

Bulldozer's shared floating-point cluster with FMA support indeed offers some advantages with legacy 128-bit instructions.

But that advantage will be short-lived once Intel adds FMA support. It would give Intel the same flexibility, and double the peak throughput at the same time. And once applications use 256-bit instructions, it doubles again!

Even if AMD doubles the width of each ALU to 256-bit, it still wouldn't match the same peak throughput per core. Also note that if the IGP is removed from Sandy Bridge, it creates room for two more cores at no extra cost (to Intel). So they can launch such an enthusiast part soon after Bulldozer, and steal AMD's thunder.

Don't get me wrong, I want AMD to deliver competitive products and Bulldozer looks like it will bring them back in the game, but I'm afraid it won't hold the performance crown for long, if at all...

 

[exar333]

#1 Question: When are you going to fire the guy who prepared this presentation?

I am running iOS 5 on my iPad right now, and it is pretty bad. Horribly buggy, it locks up all the time, dozens of buttons that do absolutely nothing. Many of the new functions require a voodoo dance of button mashing in exactly the right order to get them to work, etc.

But you sure as hell wouldn't have known that watching the presentation yesterday.

Apple still has 4 months to work out the bugs (and they will), AMD was supposed to be shipping this thing any day now. It's just embarrassing.

Well put.