Nvidia's Chen Calls for Zero Via Defects

[Idontcare]

Nvidia's Chen Calls for Zero Via Defects

In a keynote speech at the International Electron Devices Meeting (IEDM) going on in Baltimore this week, Chen said Nvidia's 40 nm graphics processor has 3.2 billion transistors, up from ~1 million transistors in 1993 when the company was founded. Although the increasing transistor count has allowed near photo-realistic moving graphics, Chen said power became a big issue, particularly at the 90 nm node "when power consumption went up so fast." Although strained silicon, power rails, sleep modes and multiple threshold voltages have kept Nvidia's 20 × 20 mm die within a ~130 W power envelope, the big concern is leakage current. "DC power has exceeded AC power for the first time," Chen said. Leakage is such an important issue for Nvidia that its transistors now have a slightly higher threshold voltage than in the past, especially for the non-critical paths.

"Over the next two technology generations we will get to 10 billion transistors easily," Chen said in a speech to ~1200 IEDM participants Monday. "We need leakage to be almost zero, or at least to have leakage be undetectable."

Chen zeroed in on vias, calling via deposition a major reliability concern. A chip with 3.2 billion transistors has 7.2 billion vias, a number "which exceeds the world population." He called on the IEDM audience, and Nvidia's main foundry vendor Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), to deliver one defect per part per billion (1 DPPB). "We have to make all the vias work; it has to be defect-free."

Variation is hurting the company's business, which depends on binning. The normal practice is to bin the best chips to the ultrahigh-performance accounts, devices that hit the mean performance and operating voltage metrics to the notebook market, and slightly underperforming chips to desktops. "The problem if the mean of the variation shifts day to day, we lose all of our ultra and some of our mobile bin," Chen said. "It creates a huge inventory of desktop chips, some of which we have to discard. This is really going to be a major problem at 28/22 and beyond. Even 1 nm variation in a CD can affect our products in a very significant way."

http://www.semiconductor.net/article/438968-Nvidia_s_Chen_Calls_for_Zero_Via_Defects-full.php

Zero leakage? Zero defects?

I noticed SOI got an honorable mention.

 

[thilanliyan]

Is it possible within mass manufacturing constraints (ie. cost)?

 

[Ika]

So basically they want TSMC to make the production process perfect so they don't fail their newest product?

 

[Acanthus]

So basically they want TSMC to make the production process perfect so they don't fail their newest product?

I think they were specifically talking about the next 2 die shrinks.

When you hit 10 billion transistors, asking for for 1 defective transistor per billion isnt all that strong of a request.

 

[jvroig]

I thought the title involved VIA, the CPU company.

When you hit 10 billion transistors, asking for for 1 defective transistor per billion isnt all that strong of a request.

Agreed. It doesn't look like it will take long to hit 10B transistors for GPUs, if Fermi already weighs in at 1/3 of that. Maybe less than a decade (does the existing tech or atleast those on the roadmap allow it?).

 

[ViRGE]

Is it possible within mass manufacturing constraints (ie. cost)?

Exactly. IDC, surely you posted this for good reason. Is what NV wants even remotely possible?

 

[Idontcare]

Exactly. IDC, surely you posted this for good reason. Is what NV wants even remotely possible?

Its laughable, but maybe only as an inside joke.

See any AMD technologists bizotching about TSMC's lackings when it comes to 40nm or beyond? Or do you see them doing their jobs with DFM (design for manufacturing) and shipping 40nm product to Newegg right now?

There are technical merits to Chen's position, of course, but usually when you berate your supply chain like that you want to do it from a position of strength so that you aren't just outing yourself as being the weakest link.

Zero defects? Won't happen, integrated circuits are tremendously low-entropy systems as it stands now and it takes an immense amount of effort and energy to reduce their entropy to the degree already attained. You want to make them even more complex (increasing the ensemble of states available for entropy to be maximized) and yet at the same time expect the entropy of the system to be even lower than it is today?

There is a reason you won't find anyone else talking like this in presentations or technical workshops. It is nonsense, perhaps Chen was just taken out of context?

Via reliability is a problem that you counter by both design rules (redundant via requirements, max wire-length requirements) as well as improved process technology.

If Nvidia is really seeing via resistance drift over device lifetime to such an extent that it impacts the reliability of the device then that certainly speaks to TSMC"s node robustness. Via stress migration is a problem for everyone and it must be dealt with as a priority during the node development stage. But via stress migration is a reality that cannot be avoided, merely mitigated and the magnitude supressed. Much like electromigration, it is there but reduced below threshold levels by a combination of design and process technology.

That said, it doesn't seem to be holding back AMD much so really how bad can it actually be?

At any rate I am not going to presume to know the whole story there or make an assumption that Chen's comments weren't taken out of context. I do imagine however that there was a number of Nvidia engineers slapping their foreheads when they read the article I linked as it does kinda make Chen out to be an idiot when taken at face value. The guy might as well said he wants future nodes to turn lead into gold and unicorns should be genetically engineered to benefit all of mankind while he's drafting his wish list of silly things that simply can't/won't ever happen.

No leakage!? Does he think these things have leakage simply because no one thought to ask for them to have no leakage until now? If you are a process engineer, or even a design engineer, these comments are comical gold.

 

[MrK6]

No leakage!? Does he think these things have leakage simply because no one thought to ask for them to have no leakage until now? If you are a process engineer, or even a design engineer, these comments are comical gold.

I'm no electrical engineer (or engineer at all, for that matter), but I was going to say the same. I would hope this was all taken out of context, because at first read it seems ludicrous. Like the companies are actually just waiting for someone to say "hey guys, make better chips" and then they say "oh, ok" and *poof* magic chips appear. Given AMD's difficulties with 40nm, I'd say good luck with that.

 

[Idontcare]

There's a pretty-picture version of this story up on semiconductor.net:

http://www.semiconductor.net/article/438968-Nvidia_s_Chen_Calls_for_Zero_Via_Defects-full.php

 

[Lonyo]

There's a pretty-picture version of this story up on semiconductor.net:

http://www.semiconductor.net/article/438968-Nvidia_s_Chen_Calls_for_Zero_Via_Defects-full.php

I think that says it all.

A larger die normally yields much worse than the combined yield of two die with each at one-half of the large die size

And that is why NV are having a fit. They picked the wrong route.

 

[Lonyo]

Its laughable, but maybe only as an inside joke.

See any AMD technologists bizotching about TSMC's lackings when it comes to 40nm or beyond? Or do you see them doing their jobs with DFM (design for manufacturing) and shipping 40nm product to Newegg right now?

There are technical merits to Chen's position, of course, but usually when you berate your supply chain like that you want to do it from a position of strength so that you aren't just outing yourself as being the weakest link.

The way the foundry business works, is it is very important to have a high volume, leading-edge customer to partner with to ramp technologies and then the rest of the customer base fills in behind.

NV can berate TSMC because they are that customer for TSMC, and will remain that customer.

 

[Idontcare]

The way the foundry business works, is it is very important to have a high volume, leading-edge customer to partner with to ramp technologies and then the rest of the customer base fills in behind.

NV can berate TSMC because they are that customer for TSMC, and will remain that customer.

Actually, interestingly enough, what is being referred to there in the quote is what is called the "qual driver" in the industry.

And for nodes prior to 40nm TSMC's qual-driver was Texas Instruments whereas at 40nm TSMC's qual driver was AMD with the RV740. (and they had to redesign that to get it to work with 40nm after TSMC changed the design rules because they couldn't otherwise hit their leakage specs...but you didn't hear AMD moaning about it publicly)

I don't know of any tech nodes or foundries for which NVidia has been the qual driver. But yes, if AMD moves GPU to GloFo for 32nm and beyond then Nvidia will soon enough get a taste of being the qual driver and then the comments they make now will be all the more real and painful.

 

[Janooo]

Chipworks has inspected products from graphics vendor ATI, now part of Advanced Micro Devices (AMD, Sunnyvale, Calif.). "The problem appears to be that when they cut a via, a residue of photoresist gets on the edge of the via, which creates a ring-shaped discontinuity in the metal," James said. "The discontinuity could create electromigration issues. We've seen the same problem on the upper metal levels on the ATI chips we've studied. It creates a reliability failure mode."

Nevertheless ATI parts work. I guess NV studies ATI's magic tricks here.

 

[Idontcare]

Intel's chips back in the day (90nm I think it was) also had noticeable metal voids in the vias if you did enough random SEM cross-sections.

It is not desirable, and certainly reliability is improved as you reduce the defect levels, but on their own they do not portend the imminent demise of the chip.

 

[taltamir]

yes, the physical constraints of reality are a PITA to work around.

Although, it is not beyond reason for him to suggest a "focus" for research for improvement. Demanding improvement be made? unreasonable; you work with what you have.
Suggesting where improvement would be most beneficial? reasonable and necessary.

 

[v8envy]

Except for the part where it's impossible to have zero defects making nuts and bolts, never mind a part as complex and requiring as many manufacturing steps as a GPU.

As IDC said, Chen may as well suggest alchemy and unicorns. Both would be a great improvement on the current state of affairs (lead remains poisonous and virgins are not highly sought after), but just as likely.