Intel's on the member list for OpenCL, but most likely only as a stop-gap solution for Havok support to play along with AMD's "open standards" initiative.Originally posted by: aka1nas
Intel's on the member list for OpenCL, what else are they going to use it with?![]()
Yes, they do. Will Larrabee be compatible with OpenCL with a generic x86 compiler? Maybe, but I doubt it'll be able to fully take advantage of Larrabee's complicated multi-core + vector design and additional LRBni extensions.Originally posted by: alyarb
then why is larrabee "going up against" openCL? does intel really expect people to not use opencl and write only for larrabee?
This is a nice summation of the branches in the timeline tree.
I would add that it needs to be taken within the context of the backdrop of Intel's pocketbook and ever-growing process technology advantage - meaning that even if Scenario 3 were the time-zero reality it would simply be a matter of time for Intel to iterate Larrabee thru die-shrinks and ISA/architecture improvements to evolve the scenario situation into becoming (2) and eventually (1).
Itanium serves as an example of such an evolution. As does the P4 -> Core -> i7 evolution. Persistence and money have a habit of doing this. Competitive advantage is rarely maintained by hope and morale alone.
The only way to argue that scenario (1) will not come to pass (eventually) is to make the requirement that Intel abandons their efforts in some capacity (always a possibility) and pulls engineers off future iterations of the product or we must make the questionable argument that NV engineers and management somehow are more crafty and clever in critically defining ways than Intel's engineers and management. (i.e. NV and Intel do an AMD/Intel A64/Prescott thing)
In a capex intensive industry such as semiconductors it is essentially a consequence of the math that tomorrow's victor will be whomever has the money (and desire) to invest today towards owning a marketspace tomorrow. There are exceptions to the rule (A64/Prescott) but in an evolving marketspace time smooths out all the exceptions and the end conclusions are just about as inevitable.
The USSR eventually went bankrupt and the west eventually won the cold the war, with the money and technology advantages that Intel has over NV and AMD it takes a rather peculiar set of boundary conditions for one to argue in good faith that the outcome isn't sort of a foregone conclusion.
Originally posted by: Wreckage
Larrabee may not even ship this year (or next). By then not only will DX11 cards be out but CUDA will have a head start measuring several years. Plus over 100 million CUDA capable machines.
Originally posted by: aka1nas
Originally posted by: SickBeast
The problem is that CUDA requires a lot of support from the industry in order to implement it. If you look at the control that intel and microsoft have had of things over the past 20+ years, I don't think NV has much of a chance of their standard taking over.
I'm not saying this is good; I'm simply being realistic.
I would imagine that Larrabee will be going up against OpenCL more than CUDA by the time that it is available. CUDA's market penetration is still low enough that many of those developers will likely just rewrite with OpenCL to pick up the other hardware platforms (I'm mostly thinking about HPC here).
There really doesn't seem to be a lot of reason to hand-code an application just for Larrabee in a world where OpenCL has already been adopted.
You completely missed the point. The point is that Nvidia's 65nm behemoth already weighed in at ~600mm^2 with 1.4 million transistors. Larrabee is already larger than that on a full node shrink to 45nm with who knows how many more transistors.... And from early indications, its still not competitive with current gen parts from Nvidia and AMD. Now do you see where Dally's "x86 tax" and design comments come from?Originally posted by: SickBeast
The thing won't be out for at least 1.5 years. At 32nm the chip won't be nearly so big. If NV can have somethign manufactured that is 570mm^2, then you damn well know that intel can do considerably better than that if they have to.
TBH I really wish that intel would release something giving us an idea as to how this chip will perform in games.
Originally posted by: chizow
You completely missed the point. The point is that Nvidia's 65nm behemoth already weighed in at ~600mm^2 with 1.4 million transistors. Larrabee is already larger than that on a full node shrink to 45nm with who knows how many more transistors.... And from early indications, its still not competitive with current gen parts from Nvidia and AMD. Now do you see where Dally's "x86 tax" and design comments come from?Originally posted by: SickBeast
The thing won't be out for at least 1.5 years. At 32nm the chip won't be nearly so big. If NV can have somethign manufactured that is 570mm^2, then you damn well know that intel can do considerably better than that if they have to.
TBH I really wish that intel would release something giving us an idea as to how this chip will perform in games.
Also, Larrabee is scheduled to launch late this year or early next, so I'm not sure what your 1.5 year comments are referring to. Actually I'm pretty sure Larrabee was already delayed once with samples originally scheduled for Q4 2008 and pushed back to around now. While its true Intel has typically enjoyed a considerable fab and process edge compared to the competition, its also becoming increasingly evident those advantages aren't going to be able to overcome and compensate for die space dedicated to x86.
Originally posted by: chizow
You completely missed the point. The point is that Nvidia's 65nm behemoth already weighed in at ~600mm^2 with 1.4 million transistors. Larrabee is already larger than that on a full node shrink to 45nm with who knows how many more transistors.... And from early indications, its still not competitive with current gen parts from Nvidia and AMD. Now do you see where Dally's "x86 tax" and design comments come from?
Originally posted by: chizow
With a die size that large at 45nm, that pretty much rules out additional transistors on this process, meaning additional performance will most likely only be possible with a die shrink and 32nm at the earliest.
Originally posted by: thilan29
Originally posted by: chizow
With a die size that large at 45nm, that pretty much rules out additional transistors on this process, meaning additional performance will most likely only be possible with a die shrink and 32nm at the earliest.
I don't remember where but I read that the pic of that wafer is actually test/prototype/whatever you want to call it Larrabee on 65nm while the actual production would be on 45nm.
Originally posted by: chizow
Larrabee Wafer Pictured in Detail - Pat Gelsinger at IDF
If Dally and Ben's comments weren't enough to convince about wasted die space, that's Larrabee at 45nm with over 600mm^2 per die with an estimated 85 dice per 300mm wafer. To put that into perspective, the original 65nm GT200 was ~570mm^2.
With a die size that large at 45nm, that pretty much rules out additional transistors on this process, meaning additional performance will most likely only be possible with a die shrink and 32nm at the earliest.
Originally posted by: taltamir
WTH! after all those slides showing how dozens of die scale almost linearly, after getting hydra, all that, and they are making a monolith? and one significantly larger than anything ever attempted by intel?
Originally posted by: taltamir
Although, maybe what we "know" about larabee is misdirection and its a more traditional GPU (in which case it needs to have a huge die), and intel is the worlds formost expert on manufacturing tech...
They're very different in the sense a CPU die is often comprised mainly of cache, which is the simplest transistor and always the first used to validate a new process node. That's very different from GPUs which are already dedicating upwards of 50% to execution units, a ratio that is only growing with every new iteration.Originally posted by: Idontcare
Intel has oodles of experience yielding >600mm^2 chips...Itanium. Beckton and Dunnington both ring in at nearly that weight as well.
Presumably die harvesting will be involved, no different for GT200 or Cell.
Originally posted by: thilan29
I don't remember where but I read that the pic of that wafer is actually test/prototype/whatever you want to call it Larrabee on 65nm while the actual production would be on 45nm.
Kind of related, but these assumptions are based on what's already been published about Larrabee. You can see in the AT review they made some guesses on clockspeed, performance (in TFLOPs), die size, process, number of cores. The big question they were unsure of was TDP, which would certainly limit clockspeeds. You can see they're pretty accurate too, and actually take into account the 65nm to 45nm and arriving at 64 cores, a number that also pops up on those IDF slides as the high-end.Originally posted by: Idontcare
I'm still trying to figure out how so many experts in this thread came to know the launch clockspeeds for Larrabee...a necessary item for making any prognostication regarding performance envelope.
Originally posted by: Keysplayr
Why would they create a prototype on 65nm? 45nm isn't just a process shrink from 65nm and needs to be reworked for 45nm, and it would seem a waste of time to create a prototype on 65nm especially when Intel has had 45nm for quite a while now and heading toward 32nm..
While it certainly is possible for that wafer to be 65nm, I don't think it's plausible at this time when 45nm has been out so long and 32nm not too far off.
:QOriginally posted by: OCguy
Speaking of IGP....
http://www.xtremesystems.org/f...howthread.php?t=222931
Your first Bold.Originally posted by: taltamir
Originally posted by: BenSkywalker
Any video encoding app would benefit without having to be patched or re-coded, for example.
That would ignore what a non x86 based alternative with comparable layout could do. Some here may demand ignorance to enter into a discussion, but in all seriousness x86 is about the poorest architecture you could imagine for this type of architecture. Decode hardware when tiny die space per core is the essence of your design goal is rather foolish. What makes this worse, far worse, is that the applications will still require a recompile in order to run on Larrabee, it isn't an OoO architecture- default x86 code would roll over and die running on it(wouldn't be surprising to see a normal processor be faster on anything with decent amounts of branching).
With several hundred thousand transistors per core wasted on decode hardware, more trasnsistors utilized to have full I/O functionality given to each core, a memory setup that is considerably more complex then any of the other vector style processor choices available Larrabee is making an awful lot of compromises to potential performance to be more Intel like then it needs to be.
Everyone seems to be taking the stance that Larrabee must have a lot going for it because of how much Intel is putting into it. Itanium anyone? Everyone with so much as an extremely small dose of understanding knew that Itanium was going to be a huge failure in the timeframe it hit. Sadly, a VLIW setup for something like Larrabee would end up being a much better option then where they are headed.
I guess, the best way to think of it is that Intel clearly sees a major movement as does everyone else in computing power. The problem is, Intel wants to take as much lousy outdated broken down crap with them as they can. We already have x86 as our main CPUs to handle that garbage, why do we need more of the same wasted die space on our GPUs? To make it so that lousy existing x86 code that isn't well suited for extreme levels of parallelization can be recompiled in an easier fashion? So let's prop up our outdated poorly structured code base for a short term gain and hold back everything else in the long term? Just doesn't make sense to me.
first accurate post of the thread... larabee is set to waste over 40% of its total space on redundant x86 decode hardware (one for each core), and for what? no SSE, no out of order... NOTHING is going to run on it without a serious recompile and recode... so why bother with it in the first place? its wasting space on a gimmick.
the way i see it, intel is banking on taking a loss (by wasting nearly half the die on NOTHING) for the chance to get x86 to become the standard, if that happens then they are granted legal monopoly status and no one may compete with them. It seems as clear as day that this could be their only course of action, intel engineers are not stupid.
I think this is why the professor in question is joining the fight... nvidia is the one company that stands a chance at braking the x86 stranglehold and potentially getting us heterogenous computing. although i wouldn't be surprised if they would just opt to displace intel as the only legal monopoly backed by stupid misapplied patent laws.
