Originally posted by: MODEL3
With 2,249X scaling for transistor number, the 5870 (40nm) was only 1,284X bigger (die size) in relation with 4870 (55nm) (334mm2/260mm2).
So the hypothetical GTX380 (40nm) with 3,15 billion transistors will have also 1,284X scalling regarding die size.
So GTX380 (3,15 billion transistors) will be 603mm2. (470mm2*1,284)
So the real GTX380 with 3 billion transistors (with the logic that you are using) is going to be less than 603mm2.
In the best case scenario will be 603mm2/3,15*3=575mm2.
I don't want to come across as trying to harass you over your estimations and logic here as it is all plausible, but I did want to quote you as a segue to my interjecting the following info regarding xtor density and why comparing xtor density between two architectures, and even comparing it to two IC's designed by the same company and using the same architecture, is a rather tricky thing to do with any degree of confidence because there are so many unknowns that we must make assumptions in regards to in order to perform such an analysis.
It is the absence of this info, the trade-off decisions made by project managers, that can result in such estimations being critically flawed because at best they will be right for all the wrong reasons.
Not that we shouldn't try, but we should be clear(er) on what it is we are assuming must be true when making xtor density comparisons. (such as "assuming the design optimization budget was the same for RV770 and Cypress, xtor density for Cypress was as equally optimized for 40nm as the xtor density for RV770 was optimized for 55nm", etc)
The following is dialogue I had with another forum member in a pm, it seems generically applicable enough to the current topic that I thought it would add value in my reposting it here in-toto. It is not meant to be all-encompassing of the subject matter of xtor density, a 600pg book could be written in pursuit of that, but it meant to communicate the salient points regarding such metrics
Die Density: Will more tightly packed transistors create more heat. Require less voltage to run? And how was ATI able to cram 900+ million transistors into such a small space and Nvidia, with 50% more transistors took up more than 50% larger die space?
xtor density doesn't really equate to power-consumption (heat) directly. Transistors are two dimensional creatures, they have a length and a width.
The length, or more specifically the minimum length possible for a given node, tends to be the metric that catches a lot of headlines. But the width is also important.
Drive currents are normalized per transistor width. nano-amps per micron.
http://www.realworldtech.com/p...ID=RWT072109003617&p=5
What is the relevance of drive current? It determines the amount of current that leaves the transistor which is then used to drive (turn on) subsequent transistors.
The higher your drive current is means the smaller (narrower in width) you can make the xtor (resulting in higher density) while achieving the same amount of amps coming out of the xtor to drive more xtors (the act of computing).
Now the architecture is what determines how many more xtors you need to drive to do your computation. This is where NV and ATI diverge and is why their xtor density can be so different.
Also drive current is voltage dependent, so you can use smaller (narrower) xtors but increase the operating voltage and get more drive current out of them that way.
Now increasing voltage will increase heat and power-consumption. So if you implement an architecture that needs lots of drive current but you want high xtor density (for lower manufacturing costs, higher yield) then you increase the voltage.
Or you could optimize your architecture to not need so much drive current and then you could use higher xtor density with lower volts.
ATI is able to cram so many xtors into such a small area because they use more narrower xtors, less net idrive per xtor, which means they either up the voltage to boost the net idrive per xtor or they implemented an architecture that is less demanding of drive currents.
(incidentally if you checkout Anand's article on Intel's choice of 8T sram on Nehalem versus 6T sram on Penryn you'll see it comes down to similar architecture vs. power-consumption vs. xtor density tradeoffs).
The architecture dependence is why you'll see me repeatedly stating in the forums that making xtor density comparisons between AMD and NV is pointless unless we know far more technical/intimate details about the architecture and design tradeoffs between Vcc and GHz that were made by the project managers.
I don't understand why if both ATI and NV use TSMC processes, why are the transistor densities so different? The transistor size of the ATI design and the Nvidia design are the same size on 40nm, correct?
The smallest xtor size (as in Lg or gate length as its called) is the same, as well as the Idrive (nA per um) for any given voltage. This is true because they both do use the same 40nm TSMC process tech.
But the architecture dictates the needs for Idrive, which then requires choices to be made in terms of voltage (power-consumption tradeoff) versus diesize (cost, yield tradeoff).
Also both voltage and the minimum gate length determine clockspeed.So if you find out you need a certain operating voltage to hit your targeted clockspeeds but you used needlessly wide xtors (too much Idrive generated from the voltage and your selected xtor width) then you are just needlessly generating power-consumption and heat. The design tools they have nowadays are good enough to eliminate much of this uncertainty though.
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