My guess is the L2 cache is tied to the memory controllers. So rather than coming up with some custom layout for that, they just clipped it to 128 bit. Otherwise they would have been committing too much silicon to the cause. That's my hypothesis.
As I mentioned before, IMOP overall it would have benefited from a smaller L2 and a bigger bus width that allowed for a 12GB card with actual memory bandwidth AND a marked increase in cahce hits vs Ampere. It would have stayed a "better" card and not had any regressions but we are not worthy of this effort this gen. Watch for the next gen to drop this blessing upon us
Again, this is an AMAZING $250 4050Ti

Or $199!?!?!?!? Wow