No 2.6GHz Phenom in Dec

[magreen]

A shred of evidence? How about the fact that not a single high end x2 was ever produced on 65nm? The Brisbanes are only for the low end. What more evidence do you need that tjeir 65nm yields stink?

 

[AlabamaCajun]

Don't just think of it as a yield problem. Also consider the edge chips that are fully formed but the core closest to the rim is shaky. Fuse it off and a trike is born. You get the full L3 cache for 3 cores. each core gets it's full cache but unfortunately the forth cache is lost with the faulty core. These odd balls are going to be sought after by the mass retailer for a cost effective multicore. I see MPCs and Home file servers eating these unique recovered assets up as fast as AMD can salvage them. Look for some special duk'es also as I'm sure that applies also but in lessor numbers. Intel won't spend the extra duckies to weld a solo-fuse' next to a duo, not a good business practice.

 

[AlabamaCajun]

Originally posted by: magreen
A shred of evidence? How about the fact that not a single high end x2 was ever produced on 65nm? The Brisbanes are only for the low end. What more evidence do you need that tjeir 65nm yields stink?

Sorry, not quite. Most of the Brisbane line ocerclocks to as much as 3.2. The problem has been in the power factor of leakage. AMD sees no need to expend money on an EOL product. The 6400Windsor and 5000 Brisbanes are pulls from the best. The only thing that sucks is the power loss. This is being adjusted in the new batches of Barcelona/Agena lines. What we don't know is if better results are coming sooner or later. Northwood and Prescott both had the same problems and even extended into the first Yonahs. Intel has gotten this fixed with Penryn showing even better results but look at all the heatsinks on the mobos still.

BTW, earlier in this thread a discussion about P4 vs XP. My friends 2.3G XP whiped the floor with my oced 3.0G northwood. That northy was a great chip for it's time but it took a bud to kill that moment for me.

 

[Viditor]

Originally posted by: magreen
A shred of evidence? How about the fact that not a single high end x2 was ever produced on 65nm? The Brisbanes are only for the low end. What more evidence do you need that tjeir 65nm yields stink?

Well firstly, you're talking about binning and not yields...
The reason that the high-end chips have been 90nm is that they are also the lowest volume, and they will be EOL in the near future.
All of the 90nm lines have been at Fab 30 since April, and Fab 30 has been slowly winding down to undergo it's conversion to Fab 38. So, Fab 30 is a perfect place to manufacture the lowest volume chips on the 90nm lines.
Besides, there was really no need to build a whole new set of masks for parts that are low volume and will be EOL soon anyway...

 

[JumpingJack]

Originally posted by: CTho9305

Originally posted by: sonoran
Ouch. And it gets worse - power consumption is an exponential function of clock frequency - not linear. So higher clock speeds would be MUCH worse in terms of power consumption.

How did you arrive at that conclusion? Dynamic power = c*v^2*f. If you increase frequency by increasing voltage, you get an approximately cubic increase in power, and if you increase frequency by improving the transistors or fixing slow circuits, you get a roughly linear increase. Are you assuming static power is the largest knob in play?

Your dynamic power equation is correct, but he must be thinking leakage, as the gate leakage is exponential in voltage as is subthreshold tunneling source to drain.

AMD's 65 nm process is a bit weak in their drive currents, so device physics dictates that to increase the switching speed (or decrease the gate delay), increase the voltage. In the dynamic term this is a cubic like function (i.e. linear in frequency, quadratic in voltage) but also exponential in the leakage term (tunneling exponentially varies with potential difference). So it is a double-whammy.

 

[JumpingJack]

Originally posted by: Cookie Monster
PHENOM X4 9500 QUAD CORE already on sale!?!?

This is one of my local NZ stores i go pick up my hardware.

Has phenoms been launched already??

Slightly confused here.

Phenoms have been appearing as a listed item in many etailers catalogs, this does not mean they have them yet... just prepping their sku catalog for launch.

 

[CTho9305]

Originally posted by: JumpingJack

Originally posted by: CTho9305

Originally posted by: sonoran
Ouch. And it gets worse - power consumption is an exponential function of clock frequency - not linear. So higher clock speeds would be MUCH worse in terms of power consumption.

How did you arrive at that conclusion? Dynamic power = c*v^2*f. If you increase frequency by increasing voltage, you get an approximately cubic increase in power, and if you increase frequency by improving the transistors or fixing slow circuits, you get a roughly linear increase. Are you assuming static power is the largest knob in play?

Your dynamic power equation is correct, but he must be thinking leakage, as the gate leakage is exponential in voltage as is subthreshold tunneling source to drain.

AMD's 65 nm process is a bit weak in their drive currents, so device physics dictates that to increase the switching speed (or decrease the gate delay), increase the voltage. In the dynamic term this is a cubic like function (i.e. linear in frequency, quadratic in voltage) but also exponential in the leakage term (tunneling exponentially varies with potential difference). So it is a double-whammy.

Do you have numbers for the Idsat compared to other processes? And numbers on % leakage vs. dynamic power at TDP vs. 90nm/other processors? I'd be interested in real (i.e. quantitative--with numbers, not words) comparisons.

 

[Phynaz]

Well firstly, you're talking about binning and not yields...

Parametric yield is the major factor in binning.

You can bin down, you can't bin up.

 

[Idontcare]

Originally posted by: Phynaz

Well firstly, you're talking about binning and not yields...

Parametric yield is the major factor in binning.

You can bin down, you can't bin up.

From my days at TI we rarely cared to distinguish the break-downs of "yield" unless we had major outlier activity going on and we needed to track down the source of the poor yield.

Binning 100% functioning chips that operated at unsellable speeds (400 MHz Niagara anyone? No, OK let's just call that poor yield then) made TI just as much money as binning chips at 0 MHz (particle causing metal opens or malformed xtors).

The accountants only cared about sellable product at the product's specs. Only the fab people who relied on hitting certain scrap parameter milestones (for personal bonuses of course) cared about making pareto's of excuses as to why product was not sellable. (I know because I was one of these fab guys for a period of time)

Having an excursion of particles causing bad yield was important to know when you wanted to go about solving a particle excursion. Having xtor parametrics going crazy because an implanter is having issues with beam current stability is important to know if you are trying to dial in bin speeds.

But only a fab guy should care about these nitty-grittys, the accountants, customers, and shareholders should really just focus on the highlights: how many sellable chips are making it to the hands of paying customers?

Everything else is just an excuse for failing to execute as well as your competitors. Go with best of breed, not with best at excuse making.