New DDR tech. 3dfx engies had a hand in development.

[Mr.IncrediblyBored]

http://www2.marketwatch.com/quotes/articles.asp?symb=TDFX&sid=42639&source=htx/http2_mw&guid={EB809777-3B10-4907-97ED-1727768EB31C}

I don't quite understand this new tech exactly. Could somebody more knowledgeable in the subject explain it, please? A couple interesting tidbits caught my attention.



<< --16 high frequency series/parallel termination channels >>


Is that something like a Rambus's dual-channel interleaving? Could 3dfx be dumping the dual-chip solution in favor of a memory interleaving tech to achieve the same bandwith? It would be a good idea. That way, a single chip board would be the competitive mainstream solution and the dual-chip would be the monster.


<< This chip was originally designed by CAMD in conjunction with the hardware engineers at 3Dfx Interactive, Inc. >>


Apparently, 3dfx engineers have had a hand in developing this. If this is going to be incorporated into Rampage-based solutions, then I have to give props to 3dfx for really going all out for their new architecture.

 

[GQ]

Ya, it's a interesting read. I wonder what card they are talking about in the following quote:

>>According to Ashok Chalaka, Vice President of IPD Marketing, &quot;This chip was originally designed by CAMD in conjunction with the hardware engineers at 3Dfx Interactive, Inc. TDFX. With the growing need for higher performance graphics accelerators that are designed to operate at speeds in excess of 500MHz, proper terminations have become increasingly critical.&quot;

&quot;We chose CAMD's CSPDDR100 since it offers the highest density among all passives by replacing 320 discrete resistors with 10 chips. Moreover, with the Chip Scale Packaging, performance is ideal at the high frequencies. This product enables 3Dfx to offer the most competitive and highest performance graphics card in the industry,&quot; said Brian Schieck, Sr. Systems Engineer at 3Dfx.<<

GQ

 

[HaVoC]

Very interesting indeed. nVidia, ATI and Matrox look to be trying to gain performance through parallelism (multiple pixels rendered per clock) Perhaps Rampage will use simpler chips running at higher speeds?

 

[Mr.IncrediblyBored]

Oh come on now. Nobody else is interested enough to make a comment?

Since nobody has explained to me what all this stuff means, I'm going to...

Boink ^^^ -KnightBreed?

...this thread to the top.

 

[rahvin]

With the minor information given it appears to be a DDR clock timing syncronization type chip. Not really sure of the implications, it could be for timing mutliple banks of DDR to the same timing or simply a simpler way of timing DDR memory. It's very unclear what with just a PR announcment...

 

[Soccerman]

this is just a new tech for terminating wires on you're PCB. it's alot more efficient then resistors in that it eliminates the reflection, and near end crosstalk (I know this terminology from Cisco networking) alot better then the resistor solution, which according to this would take up alot of room (310 resistors is alot right?).