Question New 1 nm and 3 nm CPUs coming soon to a pc near you.

[ericlp]

Wow, who would have guessed that AMD would have changed the CPU world SO FAST. The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin sometime around 2023.

Then by 2025 we will probably be seeing 1 nm or 10 Å on the books. I guess time will tell... Then what? What's next for the scale of a CPU?

1 angstrom (Å) = 0.1 nm

There are measurements smaller than 1 Angstrom - 1 picometer is 100 times smaller, and 1 femtometer (also known as a fermi) is 100,000 times smaller, and is about the size of an atomic nucleus. But there are not any technologies available to practically do anything on that kind of length scale, so the smallest useful scale is about an Angstrom.

Interesting times!

 

[Soulkeeper]

TSMC and to some extent samsung deserve most of the credit here. Also cellphones have benefited a lot from these shrinks and multi billion $$$ investments. Moral of the story, have the best partners.
I guess they'll just have to change the unit of measure at some point, like they have in the past.

• 10 µm – 1971
• 6 µm – 1974
• 3 µm – 1977
• 1.5 µm – 1981
• 1 µm – 1984
• 800 nm – 1987
• 600 nm – 1990
• 350 nm – 1993
• 250 nm – 1996
• 180 nm – 1999

 

[amrnuke]

IIRC there are huge issues once you get down to <3nm

Silicon itself has an atomic diameter of 0.2nm. So we're really pushing the boundary. I do not see 1nm being realistic on silicon because there are also massive heat density issues, which is why even for 3nm they are looking at TFET and GAA and alternative cooling solutions, because until we solve cooling, we are in a really tough place, and, 3D packaging is a hard sell as well even if we wanted more density. I mean, I've seen articles talk about heat pipes within the chip itself, somehow.

 

[ericlp]

Well, I don't really want to argue about that since, Apple, nvidia and whole host of other chip makers are fabing out with TSMC...

Also, note that Globalfoundries started by AMD, holds a patents that claim TSMC are using. So... there is that as well.

 

[beginner99]

I mean, I've seen articles talk about heat pipes within the chip itself, somehow.

I do think that is the only solution to the problem of heat density and 3D / stacking. Stacking itself is needed because as you say process shrinking only goes so far and certainly not below 1 atom diameter (and even that isn't really possible). So at some point to continue to scale we need 3D packaging and looking at power use of current desktop/server chips I see no way of putting them on top of each other without some integrated cooling. Said cooling would also solve the heat density and since in my mind that would be far more efficent cooling to what we have now could allow higher clocks.

 

[misuspita]

IIRC there are huge issues once you get down to <3nm

Silicon itself has an atomic diameter of 0.2nm.

Well it depends if you're talking about real nanometers or marketing nanometers. As far as I know, the 2 are completely separated since 4-5 shrinks ago.

 

[Cardyak]

Well it depends if you're talking about real nanometers or marketing nanometers. As far as I know, the 2 are completely separated since 4-5 shrinks ago.

Absolutely, many people are taking these nm node names as gospel and then simply cross referencing the width of metal atoms to determine the hard limit.

But in reality the node names are just marketing names, the 3nm node does not feature transistors that have measurements of 3nm anywhere (by any metric, whether it be width, gates, fins, etc...)

Despite us appearing close to the finish line due to the naming convention, we actually have a longer runway ahead in regards to scaling then many realise. This is all academic regardless, since it is not the physical limitation that will prevent future scaling, but heat and economics.

Having said that, I would not be surprised if we could get down to about 1nm (Using TSMC's marketing node names, which will probably be about on par to Intel's 2nm) - Onwards from there more of the focus will be on 3D Scaling.

 

[soresu]

Wow, who would have guessed that AMD would have changed the CPU world SO FAST. The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin sometime around 2023.

Then by 2025 we will probably be seeing 1 nm or 10 Å on the books. I guess time will tell... Then what? What's next for the scale of a CPU?

1 angstrom (Å) = 0.1 nm

There are measurements smaller than 1 Angstrom - 1 picometer is 100 times smaller, and 1 femtometer (also known as a fermi) is 100,000 times smaller, and is about the size of an atomic nucleus. But there are not any technologies available to practically do anything on that kind of length scale, so the smallest useful scale is about an Angstrom.

Interesting times!

The process node numbers currently used do not reflect actual transistor pitch size.

Also no single measurement could be used for an atomic nucleus given the large variance in atomic mass across the periodic table - it varies even between the processor elements themselves as silicon is only one element of at least 2 used there (the metal layers being copper or cobalt).

 

[amrnuke]

Well it depends if you're talking about real nanometers or marketing nanometers. As far as I know, the 2 are completely separated since 4-5 shrinks ago.

Exactly true, and admittedly somewhat irrelevant since heat density is the "real" problem. Once they solve the cooling issue, we're going to start seeing some interesting concepts.

I'm stupid, and not a microprocessor designer, nor do I have even the remotest idea of what's possible, but a vertical-fin style of CPU (smaller version of what you'd put in a PCIe slot, but on a proper CPU socket, sticking up out of the motherboard, with I/O and a chiplet on one side, and 2-3 chiplets on the other side) seems logical before even getting to 3D packaging - there would be clearance issues of course, I'm not sure if trace distances for the pins and such would be too long, and mounting the cooling solution would be awkward, but I'm sure there are ways to make it work. It would permit two-sided cooling. But I agree that on-chiplet or on-silicon cooling would be pretty awesome too.

 

[darkswordsman17]

Yeah the current stuff are marketing numbers, but give it years on that marketing process and they'll improve it close to the real numbers. We'll see where things are in about a decade, by then we might be getting the real 3 and 1nm stuff.

Which I'm not sure what marketing they'll come up with once they really can't fluff things much further. Perhaps they'll just take Intel's lead and ++++ things.

 

[fkoehler]

Sometime around 3nm, I would expect non-Si, Graphene to either start popping up in talks, or discussion about stacking, nano-tubes, etc.
Problem for the later is getting heat out from an 3d or stacked parts...
With interposers or FOVOL(sp), would be kind of interesting to see AMD start stacking chiplets bundles and going on Z axis versus route limited X/Y increases.
Considering Intel's massive treasure chest, they may pull a rabbit out of their hat. Or, if their Grand Plan never took into account AMD resurging as they have, and their 10nm hasn't, its quite possible that was left at a low level of funding with the expectation that they had another 5-10 years before needing to find the next big thing.
In that case, even Intel might not have anything available for short term horizon, and we're going to hit some odd lull.

 

[whm1974]

A link to these claims would be nice and and this smacks more of Marketing Silliness then anything valid.