Originally posted by: Nemesis 1
Now a have heard that C2D is 4 issue core Itanium 6 issue cores. K5 was a 4issue RISC runningx86 decoders.
I never ever heard of it referred to as 4 issue core, ... Speaking of issues what is being issued. and where did command come from . If you can't issue a enough commands threw the software ! . Is they why VLIW is good because the commands are longer which makes coding for apps harder. But makes for a simpler processor lower energy use while still giving good performance. Just so much good stuff out their done for X86 ya can't walk away from it.
Elbrus Cpus were Super Scalers . So its.Compilers were written to issue a lot of commands/ translations if you will at the same time.. In righting this soft ware softwear was written to do x86 also .
So now intel has decided to go super scaling with multi cores. Which to work effectively . Needs fast Compilers translating many commands at once to take advantage of all those available threads. . In order to take advantage of the cpu hardware/software . Programms have to adderess those threads. But if you lived in a perfect world a program running ten threads at once And your logic core could handle it effciently. The Compiler would have to translate all those commands at once registers . IN this case the captin of a ship is the compiler. HIS crew is the registers, Bigger the crew the better and long and lean sailors they be, It would take one hell of a compiler to manage this. A command is an issue, sofware are the commands issues are basicly 1/0 Compiler has to be well coded to handle so much so fast . I am 101 computers.
hmmm we get somethings explained here:
The "issues" that you are referring to is the amount of instructions the cpu can "fetch" and "decode" at a given cycle. The Core2Duo is 4, Itanium2 is 6.
CPUs have been SuperScaler more many many many years, this is not anything to do with more cores. SuperScaler is define to fetch and decode more than a single instruction at a time then processed in a pipeline, or something that is very close to this definition.
I am not very up to date with software terms, but a thread is not the same as an instruction. A thread is somewhat like many instructions together, i.e. a sequence of instructions.
Ok now that the facts are given i hope it helps lol
Now about the Nehalem being an EPIC CPU... well that is ridicules, i hope that isn't what you were implying? x86 CPUs are x86 CPU, the complier writes a set of instructions that are x86 instructions. The x86 CPU fetches and decodes these instructions in "hardware". The Itanium2 does all x86 stuff in software the last time i checked. Now back to the x86 CPU, after the instruction is decoded it is the CPUs job to do what ever but if you want to get technical, the x86 instructions are then turned into micro instructions which resemble very much like a RISC instruction set. But the x86 CPUs read x86 instructions and decode them as x86 instructions. I would not call the Itanium a x86 CPU because x86 software works on its system, i would not call my x86 Athlon a ARM CPU because i can run GBA games from my computer with some software called an emulator, would you.
But i do agree with you that compilers are important and they help "A LOT" in getting the best performance from you CPU but this has always been the case, especially since pipeline and SuperScaler CPUs has started 30-40 years ago...
If you think i am wrong about any of these please call me out on it.....
Anyway i hope this post helps
