Need explain about NorthBridge and SouthBridge?

[CodeName]

so, what does control NorthBridge and SouthBridge?
I found in a book that NorthBridge: Comunicates to CPU
Comunicates to RAM
Comunicates to AGP
Comunicates to PCI devices

but in another book I found that NorthBridge comunicates to CPU, RAM and AGP, or SouthBridge comunicates to PCI devices.

So where is true? NorthBridge comunicate with PCI or not?

Thank you.

 

[JSSheridan]

The Northbridge is directly connected to the AGP bus, CPU, memory, and the Southbridge. The Southbridge is directly connected to the PCI devices and the Northbridge, as well as some other devices.

On this page is a block diagram of a typical chipset. Peace.

 

[Peter]

Either is correct, historically.

Until recently, the north bridge would have CPU, RAM, AGP and PCI bus. The south bridge was a participant on this PCI bus, and did its own integrated I/O as well as bridge to ISA or some derivative for the legacy I/O.

With the advent of fast IDE, USB 2.0 and all that, this however made the PCI bus bandwidth hit the ceiling. So now, north bridges connect CPU, RAM, AGP and some proprietary chipset interconnect to the south bridge - and the south bridge now has the PCI bus controller with nothing but the PCI slots and maybe onboard PCI devices on it.

 

[CodeName]

so, both books tell true, only the time is different, am I right?

than, what to choise if I get a question: NorthBridge comunicates to PCI? YES or NO ?

Click this link and read what is written about NorthBridge.

 

[AndyHui]

Just about all current chipsets Northbridges do not connect to directly to the PCI bus, but rather with a proprietary high speed link, such as Intel's AHA, SiS' MuTIOL and VIA's V-Link.

Had this question been asked back in the days of the BX, you would have answered YES, but the answer is pretty much NO now.