NAND flash memory might get too dense at 10nm

[tweakboy]

The adoption rate of Solid state disks is fast and they are getting faster and faster. To gain higher volume sizes the NAND ICs need to shrink and that could pose an issue in the near future. Shrinking the die sizes of flash memory increases the storage density and reduces the production cost, but one major issue is that each time you shrink to a smaller process node, the ability of flash cells to reliably hold data goes down because the number of electronics in a gate decreases as well.
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[Revolution 11]

They said that transitors could never make it to the 1 micron node, and then it did. They said it could never make it to the sub-200 nm node, and it did. They said it could never go below 45 nm, and it did.

I am inclined to believe that there will be future detractors who claim something is impossible and the amazing combination of tons of money, ground-breaking research, and back-breaking work by dedicated professionals will prove them wrong again and again.

 

[BenchPress]

They said that transitors could never make it to the 1 micron node, and then it did. They said it could never make it to the sub-200 nm node, and it did. They said it could never go below 45 nm, and it did.

I am inclined to believe that there will be future detractors who claim something is impossible and the amazing combination of tons of money, ground-breaking research, and back-breaking work by dedicated professionals will prove them wrong again and again.

Shrinking the transistors is not the issue. They just become more fragile when they're smaller, meaning they endure fewer write operations. That's because writing to a Flash cell requires 'shooting' electrons through an insulator by applying a high voltage. This process inevitably causes some damage.

There's nothing fundamental that can be done about this. They can tweak a few parameters but ultimately shrinking the cells always makes them more fragile. Progress will be slow from now on, and eventually grind to a halt.

The only real hope is a totally new technology that is nothing like Flash. There are a few candidates, but most are still in the research phase and some of them even scale worse than Flash so they probably won't ever make it into consumer SSDs. Possibly the most promising technology is PRAM, for which Intel promised mass production in 2007, but Flash still outperformed it. It's also hard to displace established technology when it still has some potential (and it's comparatively cheap). With Flash definitely becoming less interesting now, the alternatives might reach commercial viability in a few years' time...

 

[Hulk]

In my opinion, shrinking the process is not the only way to bring down SSD cost. Even if process/wafer size remained the same there is still an economies of scale factor that comes into play whenever huge numbers of an item are being produced.
1. Good old fashioned big sales numbers mean that if you are able to ramp up more and bigger factories to sell increasing more SSD's then prices will come down.
2. Even at the current process technology yields will get better and other cost saving measures will be developed.
3. As more fabs open up increased competition will lower prices.

Don't worry about SSD prices coming down and performance increasing. We are just at the beginning of this new and exciting technology and we'll be seeing some huge advances on both fronts in the next few years. Who could have imagined a 1TB drive for less than $100 back in 1992 when I paid $1000 for a 1GB drive?

That is a 10,000 decrease in price/GB!

The floodgates are opening on SSD's.

 

[Deleted member 4644]

I wouldn't be surprised if SSDs plateau at around 1TB for several years. I suspect it will take a "new" technology to push us much past that point. Then again, I am not an EE and I am just speculating.

 

[Wall Street]

I wonder if any of the flash memory makers are working on adjusting the geometry of the NAND cells. For example, Intel uses Finfets for 22 nm to good results and the hard disk makers use perpendicular recording which are both examples of creatively using new layouts of the same technology to increase density. I wouldn't be surprised if Samsung or IMFT figure out how to orient the gate differently to increase density (IMFT might even benefit from Intel's Finfet tech).

 

[Yellowbeard]

IIRC, I heard at the 2011 Flash Summit that at some point below 20nm, the actual physical space in the NAND where the data sits is going to be down to just a few atoms. At some point, we're going to reach the limit of current semiconductor materials to accept and hold the charge. At some point, the size of the cell will be too small simply on an atomic level because there aren't enough atoms there to hold the charge.

 

[jwilliams4200]

Well, the lattice constant for crystalline silicon is 0.543nm , so you would have to go considerably smaller than 20nm to get down to "a few atoms".

 

[Deleted member 4644]

Well, the lattice constant for crystalline silicon is 0.543nm , so you would have to go considerably smaller than 20nm to get down to "a few atoms".

Not THAT much smaller....

 

[Yellowbeard]

Well, the lattice constant for crystalline silicon is 0.543nm , so you would have to go considerably smaller than 20nm to get down to "a few atoms".

LOL...trust me, this presentation was way over my head for the most part. Most of it was not info I need to know.

Again, IIRC, the explanation is that the entirety of the cell does not actually hold the charge. Only a portion of the cell holds the charge. And, due to the shrinks, there is potential to reduce this portion of the cell to an area that is too small to retain the charge.

 

[exdeath]

The only real hope is a totally new technology that is nothing like Flash.

STT-MRAM

Only reason nobody cares about it is that they are too busy jumping on the big easy profit NAND bandwagon. Making too much money on Flash fabs working at 150% capacity and don't want to use any modern fabs to test new technology on up to date processes.

 

[exdeath]

The floodgates are opening on SSD's.

Finally...

We got rid of floppy, 8 track tape, and VHS decades ago... stupid hard drives are the last 1950s vintage left holding back our technology.

 

[jwilliams4200]

Again, IIRC, the explanation is that the entirety of the cell does not actually hold the charge. Only a portion of the cell holds the charge. And, due to the shrinks, there is potential to reduce this portion of the cell to an area that is too small to retain the charge.

The cell size of "20nm" flash is considerably larger than 20nm.

When you see a lithography size quoted, it is usually the gate length. To a very rough approximation, the active region of a 20nm flash cell would be 20nm x 20nm x T, where the thickness T depends a lot on the specifics of the design, but it would usually be several monolayers up to several nanometers in thickness.

 

[Hellhammer]

The cell size of "20nm" flash is considerably larger than 20nm.

When you see a lithography size quoted, it is usually the gate length. To a very rough approximation, the active region of a 20nm flash cell would be 20nm x 20nm x T, where the thickness T depends a lot on the specifics of the design, but it would usually be several monolayers up to several nanometers in thickness.

The actual silicon oxide is thinner, though. I don't remember the exact numbers (can't find the PDF) but IIRC we are looking at around 10nm. It's considerably more than one atom and we'll have to go down a lot before the silicon oxide ends up being that thin.

It's not only the silicon oxide that is the problem, the number of electrons in the floating gate goes down as well. At 10nm, there would be only ~10 electrons to play with, which means any leakage could lead to serious problems.

I talked with one of Samsung's engineers during the Global SSD Summit and he said we are probably going to see one more die shrink before a new technology is introduced. It doesn't mean that NAND will be replaced but it's true that there are quite a few problems with smaller process nodes.

 

[Charles Kozierok]

Well, the lattice constant for crystalline silicon is 0.543nm , so you would have to go considerably smaller than 20nm to get down to "a few atoms".

The figure commonly used as the "node size" does not represent the smallest or thinnest structure in an integrated circuit. Gate thicknesses are already down in the "few atoms" territory, IIRC.

 

[jwilliams4200]

The figure commonly used as the "node size" does not represent the smallest or thinnest structure in an integrated circuit. Gate thicknesses are already down in the "few atoms" territory, IIRC.

Actually, as I already wrote, the quoted lithography size usually indicates the gate length. Yes, as I already wrote, the thickness of the active region is less than the gate length.

I am not sure why you and Hellhammer are so confused about that. I thought I explained it as simply as possible. I'm not sure how I could have been more clear.

 

[jwilliams4200]

The actual silicon oxide is thinner, though.

Thinner than what? You just quoted me writing that the thickness is usually between several monolayers up to several nanometers.

 

[Charles Kozierok]

Actually, as I already wrote, the quoted lithography size usually indicates the gate length. Yes, as I already wrote, the thickness of the active region is less than the gate length.

I am not sure why you and Hellhammer are so confused about that. I thought I explained it as simply as possible. I'm not sure how I could have been more clear.

Sorry, I was just trying to clarify, not contradict.

 

[Xpage]

For the 2X nm process we have 128GB be approx. the sweetspot for price/performance. For the 19nm node, we'll get to 256GB as the best pricepoint eventually, as the 19nm node scales up and yields increase.


Then the next node will be maybe 14-15nm, thus the 512GB may be the ideal spot. I'd be quite happy with 512GB SSD and a mechanical for the rest of my storage. The major issue is HDD makers not putting NAND on their hard drive sand making bybrid dirves. Seagate is the only one with momentus and their Barracuda XT hybrid drive WAS supposed to be released this year but is nowhere to be seen.

Give me a nice 2TB HDD and 256GB of NAND, say 180GB to be used with the rest as spare of redundant NAND, and I shall be happy.

 

[Ken g6]

This makes 3D NAND look more likely to me than 10nm NAND.