AMD to drop EV6 bus in upcoming Hammer microprocessors
EBN
(01/24/01 10:44 a.m. PST)
San Jose, Calif. -- Advanced Micro Devices will drop its current Athlon and Duron EV6 bus architecture for its upcoming 64-bit Hammer-series processors to allow for connecting large multiprocessing arrays, the Platform Conference was told Monday.
Bob Mitton, AMD marketing manager for workstations and servers, told the meeting here that the 64-bit processors will use a new NUMA (Non-Uniform Memory Access) bus which can link eight-way or more MPUs for high performance multiprocessing. NUMA uses AMD's projected LDT (Lightning Data Transport) controller to handle both the Northbridge memory and Southbridge I/O buses in an array of processors, he said.
Mitton asserted that NUMA is highly scalable and allows each processor to have full access to the processor bus bandwidth.
By contrast, he claimed Intel Corp.'s new IA-64 architecture for Itanium and the follow-on McKinley processors have a shared processor bus that divides the bandwidth among all the processors.
He conceded that in the NUMA scheme a CPU accessing memory at the far end of the multiprocessor array goes further to fetch data than on a shared bus, but claimed the much-faster LDT offsets any potential delay.
AMD so far has been able only to deploy a uniprocessor 32-bit Athlon version with the EV6 point-to-point bus, although Mitton said the firm is now sampling a two-way Athlon configuration with a new 760MP chipset. He declined to estimate when the 760MP will be commercially available, making a two-way Athlon configuration possible.
The 760MP Northbridge chip will be called 762 and the Southbridge chip will be called the 766.
The 762 controller will be 64-bit data width with an 8-bit ECC and support DDR memory with 2, 2.5 and 3 CAS latencies. It will support DDR PC2100 modules using 64-Megabit to 512-Mbit memory chips. It will support up to 4-gigbytes memory size, according to AMD
EBN
(01/24/01 10:44 a.m. PST)
San Jose, Calif. -- Advanced Micro Devices will drop its current Athlon and Duron EV6 bus architecture for its upcoming 64-bit Hammer-series processors to allow for connecting large multiprocessing arrays, the Platform Conference was told Monday.
Bob Mitton, AMD marketing manager for workstations and servers, told the meeting here that the 64-bit processors will use a new NUMA (Non-Uniform Memory Access) bus which can link eight-way or more MPUs for high performance multiprocessing. NUMA uses AMD's projected LDT (Lightning Data Transport) controller to handle both the Northbridge memory and Southbridge I/O buses in an array of processors, he said.
Mitton asserted that NUMA is highly scalable and allows each processor to have full access to the processor bus bandwidth.
By contrast, he claimed Intel Corp.'s new IA-64 architecture for Itanium and the follow-on McKinley processors have a shared processor bus that divides the bandwidth among all the processors.
He conceded that in the NUMA scheme a CPU accessing memory at the far end of the multiprocessor array goes further to fetch data than on a shared bus, but claimed the much-faster LDT offsets any potential delay.
AMD so far has been able only to deploy a uniprocessor 32-bit Athlon version with the EV6 point-to-point bus, although Mitton said the firm is now sampling a two-way Athlon configuration with a new 760MP chipset. He declined to estimate when the 760MP will be commercially available, making a two-way Athlon configuration possible.
The 760MP Northbridge chip will be called 762 and the Southbridge chip will be called the 766.
The 762 controller will be 64-bit data width with an 8-bit ECC and support DDR memory with 2, 2.5 and 3 CAS latencies. It will support DDR PC2100 modules using 64-Megabit to 512-Mbit memory chips. It will support up to 4-gigbytes memory size, according to AMD
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