Originally posted by: Navid
Originally posted by: chorb
For the record in the article the word "bump" describing the solder connection to the PCB is referring to the more commonly used term "Ball Grid Array" (BGA).
I have no intention of disputing or confirming the article.
But, I am curious why you say that.
Are you familiar with the flip chip technology?
http://www.amkor.com/enablingt...ies/FlipChip/index.cfm
I am by no means an Flip Chip / BGA expert, but I am an EE who works with end product.
Here are some the flaws I see in the article:
Related to this is the fact that the chip uses electricity in a non-uniform manner. Parts that are heavily used pull much more current than idle parts, and once again, those parts change over time. Some bumps may pull a lot of Amps, others may pull very few, and this again changes over time and use.
Unless Nvidia designs their chips in a completely different manner than every other chip out there, the power pins on the IC should be all internally connected; thus even when certain areas are using more power than others the current draw should be pretty close to uniform across all the power pins.
They then go on to say what I just said in the following paragraph, not sure what the aim of the argument was...
A typical chip that is a little more than a centimetre on a side might have over 1000 bumps on it, so spacing is incredibly small and tolerances amazingly tight.
When power is run through eutectic bumps, you also get an effect called electromigration. This means that some of the materials are essentially pushed around by the current, and you get voids in the bump. These voids lessen the capacity of the bump, and eventually they burn out.
So lets go with the number of pins the article says, 1000 pins on a 1cm^2 die; thats a 31x31 array (which would need an insane number of PCB layers to route to!). From my experience working with BGA parts, the spacing between pins varies, but can get very tightly packed. I'm going to make things simple, lets say the spacing between two pins is the same width as a single pin. So 31 pins with a pin spacing between them all gives a width of ~160x10-6 meters (10^-16 = um) per pin.
Citing an abstract written about BGA electromigration :
Text
It states:
The lifetime was predicted more than 20 years with the current being 160 mA/bump in 220 µm pitch cases
Using our model of 160um we are 28% smaller than the experiment, and I'm pretty sure that the graph of 'size' plotted 'against time to failure' is logarithmic; Even so we are talking at least several YEARS until electromigration would cause failure in 160um bumps.
I cannot comment on the cracking and breaking of the bumps as the die and polymer heat and cool; I'm not a mechanical / chemical engineer and I dont have much background dealing with it. I have never seen it happen on any of the boards I have worked with, but thats not to say it cant happen.
I am not a Nvidia fanboy nor partial to ATI, I just think articles like this deserve to be scrutinized as they just use big complex words to persuade the reader into believing them.