Mosfet Question

[TecHNooB]

Please do not cross post
bsobel


http://cobweb.ecn.purdue.edu/~...e%20Exams/e2fall00.pdf

Question #14

I don't understand why the answer is C.

Acording to C, Q2 is in the linear/ohmic region. But aren't the drain and gate tied together? So V_gd = 0. If V_gd > V_threshold, the device should be in saturation.

Q2 is a p-channel enhancement mode FET, so V_threshold should be some negative number. I don't see why it's not in saturation

 

[TuxDave]

I hate working with p-channel equations since everything is backwards but if you want to sit around and use negative threshold voltages and vsg instead of vgs it goes along like:

Once you see any enhancement transistor with the gate & drain shorted together, you should instantly know it's in saturation. Why? For a p-type enhancement transistor the condition is that vsd > vsg+vth (vth is negative for a pmos) and since vsd and vsg are equal, the condition is 0 > vth (vth is negative) which is always true. So if you ever see a drain and gate shorted together, it's instantly saturated ASSUMING that it's on in the first place.