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Moore's Law - Is it for real?

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Moore's law is nothing more than an approximation. The same function of transistor's per area vs. time can be described by other (not quite as simple) mathematical functions. I think most of us agree that eventually the rate of advancement is going to decrease. Perhaps it could be modeled a little more accurately by something like a logistics curve. Then again, since the average person is pushing the limits of their mathematical understanding when told to "double something", a more complicated mathematical formula that DOES allow for an upper limit (asymptote if you will) is probably far too difficult to ever become a mainstream part of our culture and vocabulary.
 
This was in a newsletter I recieved today. ´

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PRAGUE, The Czech Republic -- Speaking at the International Electronics Forum here Bernie Meyerson, chief technology officer for IBM systems and technology, said that the traditional scaling of semiconductor manufacturing processes died somewhere between 130-nanometer and 90-nanometer nodes.

It is not the first time Meyerson has spoken on the topic (see January
<http://www.siliconstrategies.com/article/showArticle.jhtml?articleID=174089
88> 19 story) but Meyerson also referred to the end of conventional
88> CMOS
which he portrayed as going the same way as bipolar logic did in the mid-1980s.

In a talk entitled the 'The transition from scaling to innovation," Meyerson expanded on his 'scaling-is-dead' theme, saying that CMOS has hit the end of the road in terms of power consumption and the industry faces a similar transition to that which it faced when moving on to CMOS from bipolar logic, but with the problem that there is no ready and mature alternative transistor logic technology waiting in the wings.

As a result the industry is already having to innovate its way out of problems.

"This lithographic definition of process technology is absolutely meaningless," said Meyerson referring to the now traditional custom of labelling manufacturing processes with a number supposed to correspond to the minimum geometries defined in the process, or the half-pitch of the most aggressive interconnect structures. "Somewhere between 130-nm and 90-nm the whole system fell apart. Things stopped working and nobody seemed to notice."

He later increased the intensity of his rhetoric saying: "Scaling is already dead but nobody noticed it had stopped breathing and its lips had turned blue."

Meyerson went on to give some technical reasons why scaling is dead the most significant one being the need to thin gate oxide to the order of a half-dozen atoms or so - with the result that not only does leakage current become hard to control but its behavior is extremely non-linear.

Meyerson produced curves to demonstrate that since 130-nm node engineers across the industry have deviated from "ideal" scaling to use thicker gate oxide, and higher voltages than would otherwise be expected to reach performance and reliability goals but with the result that there has been a dramatic rise in power density - a phenomenon that beset designs using bipolar logic made during the mid to late 1980s.

"Remember the other transistor -- bipolar -- it's happened before. Clearly a change was needed; radical innovation. In the span of a few years IBM moved from bipolar to CMOS. When we moved to CMOS it was mature, had existed for 30 years. The problem now is there is no other 'magic' technology for us to ride."

Instead of scaling industry has to innovate, Meyerson said or rather it would continue to scale but "60 to 70 percent of the benefit of each new generation of manufacturing process would have to come from innovation.

Meyerson also made the point that IBM has been pioneering many of the innovations that will be introduced; silicon-on-insulator, strained silicon and FinFETs he classed as relatively near term innovations. He also discussed molecular electronics performed with the metastable movement of carbon monoxide molecules moving on a copper surface as an "out-of-the-box"
innovation.

With circuit dimensions of 12-nm by 17-nm something like 500 billion circuits can be contained within a square centimetre, Meyerson said and computational power efficiency is about five orders of magnitude better than state-of-the-art silicon. A couple of drawbacks that Meyerson admitted to are that the circuits are one-time-usable and only operate at liquid helium temperatures.

"The real roadmaps going forward are going to be innovation roadmaps, not lithography roadmaps. It's not just lithography that is driving progress,"
Meyerson said.

Meyerson also stressed that hardware as a platform for software was no longer an adequate vision of modern electronics, which had to be designed holistically from the atoms up to the supervisory software. He then cited the latest Power5 processor, with its dynamic thread-dependent voltage control, as an example <http://www.siliconstrategies.com/article/showArticle.jhtml;?articleId=19400
126> . This allows major circuit blocks to be slowed down by reducing
voltage to optimise power consumption.

"Technology has already transitioned from scaling to innovation. It came across us very suddenly, but the balance has already tipped in favor of innovation. We used to see 30 percent CAGR in clock frequency. I'd be shocked if you see 15 percent from now on."

In a question and answer session at the end of his talk, Meyerson said he expected the change would have profound effects on the foundry industry.
"The foundry industry used to be able to purchase scaling tools four months after an industry leader had revealed something and take the benefit. But if you only get 40 percent of the benefit from scaling, suddenly the foundries have to do R&D like they never had to do before."

When asked if the International Technology Roadmap for Semiconductors (ITRS) had been the enemy of the semiconductor industry by preserving an illusion of endless scaling, Meyerson said he wouldn't be too hard on the ITRS, because their curves were the industry's curves, but concluded: "Basic science got pushed to the back by people who like to draw straight lines."



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Painkiller, what helps my argument is that Moore's Law, as it's referred to, states transistor density will double every 18 or so months. For over 40 years, this has been true.
What the fvck are you disputing?

Intel and AMD have said publicly they expect Moore's Law to still be valid for another 20 years.
You're right and 2 of the largest chip makers are wrong?
 
There is simply no way transitor density will continue to double every 18 months; in fact I think we have already seen the end of that (read the text I posted above).

The performance will probably continue to improve using other materials, designs (dual core for example) etc, but there is simply no way to shrink Si transitors much more.
We are also really pushing the limits of photolithography, maybe we can get down to 30 nm linewidth or so using tricks like immersion lithography etc but in order to go below that we need new sources of light and I can't see that happening any time soon.

 
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