Modern bus link between North- and Southbridge

[Benedikt]

Hi,

I have some questions about varios new buses for connecting the north- and southbridges of modern chipsets (Hub-link, V-Link, Hypertransport ... ):
I heard some ports/connectors, that such a new southbridge offers, are directly connected to the interface, not via the PCI-bus; e.g. the IDE-Ports. This should be good for getting the load off the PCI-bus !?
Now my question(s):
1.) Is this true, are the IDE-ports directly connected to the chipset link?
2.) Which other ports are connected directly? Firewire ports (if they are embedded in the southbridge)?
3.) Is a speed improvement really noticeable for faster direct chip-to-chip links? Or would the PCI-bus be enough at modern PC's, if you don't use Gigabit Ethernet or RAID arrays...?

Thanks for your help!

B. W.

 

[Peter]

Getting the south bridge internal stuff off the PCI bandwidth is the whole point about making a higher speed inter chipset link. With twin UDMA-100 or even -133 channels, up to six USB ports, sound, softmodem and maybe more, the 133 MByte/s PCI bus was already choking the south bridge alone, let alone have anything left for add-on cards.

So yes, everything inside these modern south bridges is off the PCI bus.

SiS btw identified that problem much earlier on, and have had the biggest bandwidth eater, the IDE channels, in the north bridge (!) ever since their last iteration of 486 chipsets.

regards, Peter

 

[Sahakiel]

<< SiS btw identified that problem much earlier on, and have had the biggest bandwidth eater, the IDE channels, in the north bridge (!) ever since their last iteration of 486 chipsets. >>


Maybe I'm an idiot, but I don't see how that's possible. I've never seen it.
Besides, I look at the layout for a random SiS chipset (say, 645) and it shows the IDE channels connected to the southbridge. I look at the single chip solutions, it's hard to tell (impossible for me) what's northbridge, and what's southbridge, but after reading a few descriptions, I'm assuming the layout is still the same with the EIDE connected to southbridge.

 

[Jayllo]

yea, I had a question about the north-south bridge. if for example you have intel hub architecture 1.0 (266m/b north to south connection) and you have 66mhz 64bit pci slots (supposedly the i840 has 800 MB i/o) and I saturated the connection. Would the peak connection for data transfter cap at 266mb? If so? Would someone explain the purpose of having 800 i/o but only 266 being able to transfer at once?>

 

[Peter]

Sahakiel, look at the block diagrams of earlier two-piece SiS chipsets, 5591, 600, 530, 620. They all have the IDE
channels in the north bridge, their accompanying 5595 south bridge doesn't even have IDE. Why should that
not be possible? Their 496/497 chipset, last to appear in the 486 era, had this kind of arrangement already,
not sure if its predecessors did so too.

SiS didn't make much of a deal of it until recently, when they started pushing their chipsets into the high
performance area. Now that their two-piece chipsets have a high speed interconnect (533 MB/s), the IDE channels
have moved over into the south bridge part, but still have their own dedicated thread on the stupidly named
MuTIOL multi-threaded interconnect bus. In the single-chip sets, this is true also, but the (chip internal) MuTIOL
runs at 1.2 GB/s total there.

Jayllo, welcome to the wonderful world of marketing vs. reality. You might have busses that add up to 800 MB/s,
but in real life on i840 they step on each other's toes. That's why "real" server chipsets mostly have peer PCI busses
coming out of the same northbridges, some even allow having two northbridges in parallel for a total of four
PCI busses, with a fifth one originating on the south bridge. (See, Sahakiel, there are all kinds of "weird" bus and
bridge arrangements out there, mostly from smaller companies that think outside the box.)

regards, Peter

 

[Jayllo]

Thanks for the clarification Peter, I was looking at the block diagrams of a Tyan Serverworks board and it seems to illustrate what you said very well. http://tyan.com/products/assets/images/s2688_3pci.gif