Memory Cycles

[MadAd]

6ms access time of a stick of ddr describes how long one call and response loop of a read or write takes, from cpu to memory back to cpu ok? .... And one read or write is made up of several command rate (1T) cycles, broken into 4 main areas, Cas, Ras to Cas delay, Ras Precharge and Active to Precharge delay yeah?

But a complete memory access sequence neednt necessarily take the same time (or does it?).

Anyway, when working it out, would I be correct in assuming that tRas is a compulsory event, tRP does not need to occur if the same row is accessed again, tRCD does not need to occur if no column change is needed, and CAS is also a compulsory event?

With memory with fast timings of say, 2-2-2-5, worked out as above that gives just a tRAS+CAS latency penalty of 7 cycles. Therefore, for fast ram, 7 cycles is 1 access time which is 6ms. (But for say, slow old 3-4-4-8 ram, 11 cycles minimum for tRAS+CAS.

Have I lost a plot somewhere or is that acceptable as an explanation of an access time? So despite 6ns being a fact that you can measure, this means the 1T command rate of a memory subsystem (that we refer to so much in overclocking and reviews) is not just dependant on what speed ram you bought, but also the nature of the memory event?

My other half a brain wonders if perhaps there is a penalty for finding out there is nothing to do at tRP and tRCD time, perhaps it still has to wait the advertised time till it moves on to the next event? Doesnt make sense tho. Or perhaps there is a more definitive meaning of 1 access when nanoseconds are measured? If someone knows it could they share please?

Also I wonder (ask) if there is any additional delay when calculating access time, from the CAS event making the result available to the wire, to the CPU acting upon it (kinda like a 5th event, like tRCD in reverse)?

Thanks for any pointers.

Ad

 

[itachi]

Originally posted by: MadAd
6ms access time of a stick of ddr describes how long one call and response loop of a read or write takes, from cpu to memory back to cpu ok? .... And one read or write is made up of several command rate (1T) cycles, broken into 4 main areas, Cas, Ras to Cas delay, Ras Precharge and Active to Precharge delay yeah?

no, command rate only applies following assertion of the chip select pin..

But a complete memory access sequence neednt necessarily take the same time (or does it?).

Anyway, when working it out, would I be correct in assuming that tRas is a compulsory event, tRP does not need to occur if the same row is accessed again, tRCD does not need to occur if no column change is needed, and CAS is also a compulsory event?

yea.. ram can be written and read as pages.

With memory with fast timings of say, 2-2-2-5, worked out as above that gives just a tRAS+CAS latency penalty of 7 cycles. Therefore, for fast ram, 7 cycles is 1 access time which is 6ms. (But for say, slow old 3-4-4-8 ram, 11 cycles minimum for tRAS+CAS.

going from a row select to the column select has an average delay of tRCD.

 

[imported_whatever]

iirc, your explanation is pretty wrong. since the RAM does not cycle at 1ns, each of those things takes longer than that. 6ns RAM cycles at 6ns, meaning 166 MHz. Each of the timings is measured in clock cycles, NOT ns.

 

[Peter]

The nanosecond number is the CLOCK PERIOD, 1/f where f is the operating frequency. Full access cycles at least involve a column address procedure (on an open page), or a full blown addressing cycle including row and column access.

Typically, the best north bridge based RAM controllers have a latency of 12 to 14 RAM clocks for a full addressing procedure, while AMD's Athlon-64 homes in at much less than that, only 7 to 9. After the addressing, the actual data are processed in a burst - and this is where data are transferred every clock, with DDR RAM every half-clock period. (This is why 200 MHz DDR does not equal 400 MHz: DDR technology does NOT speed up the addressing. Where SDR RAM took 12+8=20 cycles to transfer a full cache line, DDR takes 12+4=16. That's far from twice as fast.)
Burst sizes range from 8 to 32 cycles.

 

[Peter]

... and if you want diagrams, I recommend you download any random DDR RAM datasheet from Samsung.

 

[MadAd]

Thanks for the replies all

itachi - my head is still hurting trying to understand what you wrote Im sure it makes sense to someone that understands all this but im a definate beginner, trying to grasp the basic sequence.

whatever- yes I know ram does not cycle at 1ns- there would be no need for ratio calculations if that were the case.

Peter - The 6ns figures that get quoted on ram is infact not access time? You mean 6ns is the command rate (1T) and not the time it takes for one complete read or write? Thats what most sites seem to suggest so i took that for granted. So the whole sequence of an access is around 6ns (for ddr).

So if a column address event (tRCD) is compulsory, then according to my fast ram model above, that would add 2T to the minimum execution time of an access, making it 9T = 1 access?

"north bridge based RAM controllers have a latency of 12 to 14 RAM clocks for a full addressing procedure" Hmm, would you call that one access too?

Dont you mean 200SDR? I understand what you mean, ddr on the other half of the sine wave but didnt realise there was a high penalty with it- what is the 12 in your sum? tRAS?

 

[MadAd]

on a further thought, is that why intel stopped at quad pumping? that would be 12+2? Not really a great improvement, going to oct pumping would dimish the return further to 12+1, hardly worth the R&D?

 

[Peter]

Intel doesn't do quad pumping on the RAM. They do on the CPU FSB, but not on the RAM. (That's why you pair a 200 MHz QDR FSB with twin 200 MHz DDR RAM busses for best performance.)

Worst case, you'll spend those 12 to 14 clock periods (6ns each) until your first data arrive. Further data from adjacent addresses will arrive at one per clock on SDR, and at one per half-clock on DDR RAM.

What's taking so long is passing the access out the CPU, down the FSB, through the northbridge and back out the RAM bus - and then command setup, row+bank address, column address latencies adding up before the data start arriving and travel back up through the northbridge, out to the FSB, and finally into the CPU. That data stream will flow through at one per clock, one per half-clock, or even two per half-clock if you're running twin DDR RAM busses in parallel.

The AMD64 architecture is a lot faster because the path from the CPU to the RAM and back is shortened - not because it were any faster on the RAM bus itself.

 

[Peter]

Now will you look at a bus timing diagram already *pokes MadAd with pointy cushion*

http://download.micron.com/pdf...dr/512MBDDRx4x8x16.pdf