Meaning of process technology

[TGV]

Hey guys, i was just wondering - all the time i hear about new process technology's has been invented and i as a EE know what it means when we are talking heat, power consumption and so on. My question is wether it decides transistor width, length og just the space between conducting lines?

In my opinoin it decides the length(ref. Reference)

But what do you think?

TGV

 

[Harvey]

I believe it has to do with all of the problems associated with shrinking geometries, including the smallest feature dimensions that can be obtained and the mechanical, thermal and other phyisical and electrical properties of the materials.

 

[TGV]

I am fully aware that it decides the smallets feature dimension that be can used, but how does that relate to transistors? And does it relate at all?

 

[fffblackmage]

I thought the process tech (65nm, 55nm, 40nm, etc) referred to transistor width. or maybe im confusing that with something similar...

 

[TuxDave]

Originally posted by: TGV
I am fully aware that it decides the smallets feature dimension that be can used, but how does that relate to transistors? And does it relate at all?

It equates to drawn transistor length. This is different than the effective channel length. You can see the two differences here:

http://www.realworldtech.com/i...es/CMOSintro2-fig1.gif

Ldrawn vs Leffective.

 

[esun]

I was told by a professor (and it seems to be corroborated by this article: http://www.solid-state.com/art...isplay.html?id=236446)) that it refers to the DRAM metal half pitch. The pitch would be the minimum spacing between two adjacent metal lines (from left edge to left edge). Half of that is the technology node (45 nm, 32 nm, etc.).

EDIT: To clarify, this means it is not directly related to channel length (drawn or effective).

 

[TGV]

Its quite funny how this is not clearly defined, but from this article(ref):

Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (FETs). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some may be smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

I have asked my professor in analog electronics and he is sure that it refers to minimum transistor gate length - but not sure if its drawn or effective.

thanks for all your answers people!

 

[esun]

It is definitely not the effective transistor length (which can be substantially smaller than the process). Historically (i.e., in 0.25 um and larger technologies) it did refer to the drawn channel length (which in those days was about the same as the effective channel length anyway). With deep submicron technologies, however, the DRAM half pitch definition is a better measure.

If you want the best answer, I'd ask someone in device processing, not in analog electronics. Actually, if you look at the 2007 edition of the ITRS:

http://www.itrs.net/Links/2007ITRS/ExecSum2007.pdf

You'll see an explanation of this on page 17. They indicate that the DRAM half pitch is just one measure, but it's the one they use (and used to refer to it as "Technology Node", although they no longer do to avoid ambiguity).

Also refer to the table on page 76. Note that for a DRAM half pitch of 65 nm (aka the 65 nm technology node), the drawn channel length is 42 nm while the physical channel length is 25 nm. Clearly the technology node does not refer to the channel length.

 

[TGV]

Now this is getting way out of hand Esun, from your document its shown that MPU Physical Gate Length (nm) << DRAM ½ Pitch (nm) (contacted) which defines the process technology.

As you mentioned, its apparently only a historical definition regarding transistor channel length. So we can conclude that they no longer use the process technology size for anything other than DRAM half pitch. And from DRAM half pitch, other features are sized.

The friend i help has three answering possibilities(in which we must assume one IS correct - maybe a bit vague - but its a quiz)

1. Minimum transistor gate width
2. Minimum transistor gate length
3. Minimum wire spacing

So.. what do you think?

 

[esun]

I think the professor sucks at writing questions. Honestly, if this is an introductory electronics class (and from the question I'd guess it is), I'd guess the professor intends the answer to be 2 (just because that has become conventional wisdom to some extent). However, 3 is more technically correct (although "wire" is so vague a term as to be almost useless in this context).

If you were to put either 2 or 3 down I think you could argue for points. If you do answer 3, you could cite ITRS 2007 (although you'd have to argue that "wire" refers to Metal 1 in a DRAM process) which I doubt the professor would want to argue with.

 

[TGV]

Its not an introtuctory quiz for EE, but its an general competition to win tickets to "Roskilde Festival, Denmark". As an EE; i found the question to be so vauge that it was hard to answer - because (as i have emailed to them) neither of the possibilities are correct! I concur with you on the fact that they want us to answer 2.

Seen from a factual point of view - its annoying. From what i have found out (from you and other sources), process technology referes to DRAM half pitch which is half the distance between to adjacent memory cells en DRAM. Of course then the distance must depend of whatever such memory cell holds! It holds a transistor and a capacitor (ofc) - and hence it does really not realte to the actual gate(channel) length at all. Historiacally, it has been so - and i really think that what they mean is:

Average drawn transistor channel length

Thanks for your participation esun

 

[TuxDave]

Originally posted by: esun
It is definitely not the effective transistor length (which can be substantially smaller than the process). Historically (i.e., in 0.25 um and larger technologies) it did refer to the drawn channel length (which in those days was about the same as the effective channel length anyway). With deep submicron technologies, however, the DRAM half pitch definition is a better measure.

If you want the best answer, I'd ask someone in device processing, not in analog electronics. Actually, if you look at the 2007 edition of the ITRS:

http://www.itrs.net/Links/2007ITRS/ExecSum2007.pdf

You'll see an explanation of this on page 17. They indicate that the DRAM half pitch is just one measure, but it's the one they use (and used to refer to it as "Technology Node", although they no longer do to avoid ambiguity).

Also refer to the table on page 76. Note that for a DRAM half pitch of 65 nm (aka the 65 nm technology node), the drawn channel length is 42 nm while the physical channel length is 25 nm. Clearly the technology node does not refer to the channel length.

In school when I designed on a 90nm node, the drawn channel length and process node were equal. And I can assure you that down to 45nm it's the same. I agree that process technology should represent the device density that the process should achieve and so if the drawn channel length is 45nm but the DRAM half pitch is 65nm, it is better to represent it as 65nm.

 

[WildHorse]

i understood it as the combined implementation of the library of physical structures to perform various circuitry functions plus the library of logic structures. Always shrinking physical sizes, always improving logic. smaller smaller smaller

 

[gruhl]

Different companies use different metrics when defining process pitch (Leffective vs Ldrawn). For example, 45nm for one company may mean Ldrawn while it could mean Leffective for another. Forget DRAM size and other metrics you guys are trying to come up with... process pitch is simply the smallest structure that the litho process can support. "Process" covers a whole range of things (number of metal layers and their performance characteristics, types of transistors that are available, restrictions for how certain elements are drawn, etc.).

 

[IHateMyJob2004]

To those of you into processor design. Get VERY GOOD GRADES and do internship/co-ops that are relevant.

If I could do it all over again, I would have done things much differently. I loved processor design in school but it is a tough field to get into. My grades did not cut the 3.5 GPA req't that IBM had.

I do software now and like it. I just wish things turned out differently.