Max Mhz speed - what causes it?

[Harabecw]

Hullo! I've been wondering about this for some time.
Lets take video card memory modules. at some point when you OC they stop working or give out errors all over the place. same with CPU's, actually.

What determines the max speed a certain cheap can reach? A P4, for example. what does the difference between 0.18micron and 0.13 micron do exactly?

I'm sure everyone around the forums can safely say "smaller process will allow higher speeds", but how?


Thanks in advance

EDIT: sorry for the poor title, can't think of a better way to say it

 

[CTho9305]

Disclaimer: this isn't the standard explanation... someone else can give you that. I'm also tired

Think of a circuit like a bunch of little switches, with resistors and capacitors between all the switches. The resistors limit how much current the switches can supply, and the capacitors are the load that has to be switched from 0 to 1 and back.

Wider wires and switches act like smaller resistors, so you can push more current into the capacitors. Shorter switches also act like smaller resistors.

The number you referenced (.18u, .13u) is the minimum length you can make a transistor. That means there is an upper limit on how much current can be driven into the capacitors (because there is a minimum resistance a certain length can give you). In order to change a line from 0 to 1, the switches have to charge up the capacitors to whatever the threshold voltage is.

The reason that P4s and Athlons have different top speeds has to do with the number of switches hooked up in a line - each one adds the delay worth of charging its capacitors. The standard line is that Athlon does more work per clock cycle with its longer lines than the P4, so each cycle has to be longer.

edit: Behold my crude art. The top-left box is the circuit for an inverter. Its output is the opposite of the input. Below it is a model of the circuit, showing what limits its performance. (Note that each transistor input has a capacitor which I am ignoring.) The top-right box shows where most of the capacitance comes from that the output of one gate sees. You can see the gate length - the longer it is, the longer the path that current has to travel and the more resistance.

Hopefully this makes sense...

 

[TDSLB]

ok this is what I got...

basicly what your saying is that a smaller die size provides smaller switchs with less resistence and therefore greater voltage and current?

 

[Lynx516]

What CTho9305 has said so far is true. The smaller the transistor the faster it can switch and so a higher clock can be reached. However there is a nother reason specific to CPUs, the architecture. Basically a CPU does things in small stages. This is because you have to swtich x number of transistors to get the answer out of the unit BEFORE the rising edge of the next clock. The concept of having to switch one switch after another is called signal propergation (spelling?). So the more work in each stage of the pipeline (the all the stages of put together) the less time the signal has to propergate between each transistor before the next clock.

Lets take a real world example of the Athlon XP and the P4. The P4 has lots of stages in its pipeline, (over 20) while the Athlon has about 13 (off the top of my head so dont quote me). This means that the Athlon has to do more in each stage of its pipeline per clock and therefore cannot reach as high clock speeds as the P4 which has to do less.

Think that about covers it.

 

[PrinceXizor]

Originally posted by: TDSLB
ok this is what I got...

basicly what your saying is that a smaller die size provides smaller switchs with less resistence and therefore greater voltage and current?

The size of the die has no bearing (at least in the context of what has been discussed). For example, I could make a CPU with 10,000 transistors on a .15u process that will have a much smaller "die" than 1,000,000 transistors on a .13u process. The term "die" shrink is what you hear when an existing .15u design has been "shrunk" so to speak to .13u design. Therefore the die size is reduced because you have XXXX # of tranistors that are .13u wide instead of XXXX # of transistors that are .15u wide. Hope this helps. Someone eles would probably explain it better, but u are stuck with me

P-X

 

[Harabecw]

well, then its a given that the XP "does more work per clock cycle" it can compare to a specific P4 while being slower in the mhz department (like AMD's...not so perfect system).
But, why does that fact prevent XP's from reaching very high clock speeds?

 

[rjain]

The fact that the athlons do more per clock means that it takes longer for them to do that work. Therefore, the clock cycle needs to be longer. Also, there's the issue of volume and binning that's explained in the article from realworldtech.com about progressing beyond the x86. Basically, the more processors you make, the more feasible it is to bin them into more speed grades. Then, of course, your top speed bin will be faster than otherwise.

 

[CTho9305]

basicly what your saying is that a smaller die size provides smaller switchs with less resistence and therefore greater voltage and current?

Voltage is fixed. Resistance and voltage determine current (V = I*R), so if your design runs on 1.6V, then switches with less resistance (smaller R) will mean more current (bigger I). Imagine capacitors like water balloons that you fill up for a 1 and empty for a 0. The more current you can push into / pull out of the balloon, the faster you can get it to be either a 1 or 0.

Originally posted by: rjain
The fact that the athlons do more per clock means that it takes longer for them to do that work.

Almost... there is more than one way to do each task though. You could design an adder that uses the algorithm you learn in elementary school (easy, but extraordinarily slow) and have it take 2 clock cycles (do half of the addition in each cycle), or a carry-lookahead adder that takes 1 cycle and clocks 10x faster (carry-lookahead is much faster as you add bigger numbers). The first design does less work in each cycle AND takes longer because of a poor choice of how to add numbers. However, your point stands

 

[BruceLee]

Originally posted by: Harabecw
But, why does that fact prevent XP's from reaching very high clock speeds?

Skim through some articles about CPU architectures on the front page. Anand gives a very detailed description of why exactly each architecture has its advantages and disadvantages. In short, the reason you don't get the high frequency on the AMD chips as you do with the Intel chips is because the Intel chips usually have a longer pipeline (http://anandtech.com/cpu/showdoc.html?i=1815&p=4). Like I said check this page out, or others in the article, to get more info on a typical CPU architecture, and why each CPU has its advantages and disadvantages.

 

[rjain]

Ohm's law (V=IR) doesn't apply to semiconductors, btw... The "effective" resistance of a semiconductor changes with current, but it works for explaining this behavior.

And yes, my comment about doing less work in a cycle doesn't delve into the benefits of a deeper pipeline (nor does it even touch the surface of the drawbacks, which are a much much more complex issue...). For the full story, do as BruceLee said and read some of the wonderful articles on this site.

 

[Lynx516]

Originally posted by: CTho9305

basicly what your saying is that a smaller die size provides smaller switchs with less resistence and therefore greater voltage and current?

Voltage is fixed. Resistance and voltage determine current (V = I*R), so if your design runs on 1.6V, then switches with less resistance (smaller R) will mean more current (bigger I). Imagine capacitors like water balloons that you fill up for a 1 and empty for a 0. The more current you can push into / pull out of the balloon, the faster you can get it to be either a 1 or 0.

Originally posted by: rjain
The fact that the athlons do more per clock means that it takes longer for them to do that work.

Almost... there is more than one way to do each task though. You could design an adder that uses the algorithm you learn in elementary school (easy, but extraordinarily slow) and have it take 2 clock cycles (do half of the addition in each cycle), or a carry-lookahead adder that takes 1 cycle and clocks 10x faster (carry-lookahead is much faster as you add bigger numbers). The first design does less work in each cycle AND takes longer because of a poor choice of how to add numbers. However, your point stands

Not quite true. As the work you are using is not the correct type of work. The work is realy number of transistors switched threfore the first one will do more work as it needs more transistors

 

[CTho9305]

Ok, agreed

 

[Lynx516]

My god someone actualy agrees with me for once