BTRY B 529th FA BN
Lifer
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Thankfully, exploitation of the vulnerability requires low-level access to the host system - meaning that an attacker wishing to make use of the flaw to implant malicious code in ring -2 would already need to have ring 0 access, the highest level of access typically available to user-level code.
Also this part means your system is already compromised
Intel VT-d and AMD-V were considered Ring -1 in some papers, so that's where the Hypervisor runs. And as far that I recall, Ring 1 and 2 are barely used in the x86 world since for portability reasons with other architectures which have more simple Ring designs, they use only Ring 0 and 3.A VM shouldnt run in ring0. They run in ring1.
It may be different between certain VM hypervisors tho.
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Intel VT-d and AMD-V were considered Ring -1 in some papers, so that's where the Hypervisor runs. And as far that I recall, Ring 1 and 2 are barely used in the x86 world since for portability reasons with other architectures which have more simple Ring designs, they use only Ring 0 and 3.
I recall having suggested a year or so ago that SMM was related to how Intel programs Processors to enable/disable feature bits and such, when a Core i5 that magically had Hyper Threading turned on appeared on overclock.net.
I mean, VT-x and AMD-V. I think you should figure it out that I made a typo there.VT-D/AMD-Vi is very rarely used.
Edit: It will be interesting to see if AMD CPUs are vulnerable to this.
That's why all my machines are Itanium (although my Itanium "laptop" does get a little heavy).
Great battery life with the generator and 5 gallon jerry can accessories though.
This is what I found on Wikipedia (do you remember now? :biggrin: ):(TBH, my memory is pretty fuzzy, I don't remember if the 386 even had SMM.)
It was first released with the Intel 386SL.[1] While initially special SL versions were required for SMM, Intel incorporated SMM in its mainline 486 and Pentium processors in 1993. AMD copied Intel's SMM with the Enhanced Am486 processors in 1994. It is available in all later microprocessors in the x86 architecture.
Make a program that will unlock hyperthreading on older intel processors 😀
The guy that talked a lot about that was Charlie from The Inquirer (Now he is on SemiAccurate).Nah, make a program that will unlock that "reverse-hyperthreading" mode that everyone was talking about before Conroe arrived, but never showed up for some strange reason!
The guy that talked a lot about that was Charlie from The Inquirer (Now he is on SemiAccurate).
There is a point in SMM. It is pretty much undocumented and can be used for a lot of nasty tricks. Since Intel uses just a handful of physical dies for a thousand different SKUs, there should be an easy way to program their specs to them AFTER the binning process. It may even be by using a special Socket that make contact with pins that aren't used on the standard version and enables the model specific registers write mode. However, when Intel launched their "CPU upgrade" pilot programs some years ago that could unlock features on some specific CPUs, I got obsessed that there is a pure Software way to deal with this.