Mark Bohr: Intel can do 7nm without EUV

[ShintaiDK]

I've been wondering that myself.....and what types of chips benefit the most from EUV compared to 193nm immersion.

Since I have to imagine EUV (at the beginning stages of HVM adoption) reduces defects at the expense of throughput: Maybe a processor with a high amount of heterogeneity (like an SOC) is a better choice for application of EUV at critical layers than a CPU or GPU with a lot of repeated units (ie, a chip that can more easily be binned if one or more defects occur).

Does that logic follow?

EUV is supposed to reduce the cost on all chips. The lack of EUV is esentially the reason why transistor cost for TSMC and Samsung foundries only goes up after 28nm. And the lack of EUV is why the foundry business customers is starting to recycle nodes like 28nm as never before.

 

[cbn]

EUV is supposed to reduce the cost on all chips. The lack of EUV is esentially the reason why transistor cost for TSMC and Samsung foundries only goes up after 28nm. And the lack of EUV is why the foundry business customers is starting to recycle nodes like 28nm as never before.

The reason I asked that question is because I have read some foundries have taken orders of EUV scanners and plan to use them in production. This even though throughput is no where near where it was originally envisioned to be.

 

[Idontcare]

The reason I asked that question is because I have read some foundries have taken orders of EUV scanners and plan to use them in production. This even though throughput is no where near where it was originally envisioned to be.

If you (the royal you) want to approach the topic sensibly then you have to start with the understanding that there is reality and then there is journalism/hypeism/spinism/etc.

Those in the media have a job to do, and that job is to generate enough revenue so as to pay their bills (both the media company's bills as well as the mortgage and other bills of every article author of said media outlet).

What pays the bills better than a divisive argument, pitting two opposing situations against one another as if it was a binary environment where two men enter, one man leaves.

So my advice to any industry outsider (most anyone on this forum) who is approaching the topic of EUV as it has been presented to them through the intentionally shaded glasses provided courtesy of modern-day 'anything for the page impressions' tech journalism is to accept that you are being sold a narrative, a nicely packaged story line, that keeps their paychecks coming in their tech reporting jobs...and that requires the author to seek and sow high drama if they want their paychecks to keep coming.

The reality of EUV down in the trenches is far less dramatic, far more stoic, and far more measured than what you will ever be lead to understand from the superficial realm of tech reporting. It is the nature of the beast when you (the royal you) don't want to directly pay for the information that you want to receive.

So what happens is that reality, the early and limited production use of EUV, will seem to come in spits and spats at seemingly irregular and disjointed timing. It seems like that because it is reported like that, not because it really is like that.

If the state of EUV were publicly reported in the degree to which it is a smoothly evolving progression of iterative development events then it would be as dull as watching paint drying, or as dull as reading about the monthly progressions of node development for any advanced process node for IDM and foundry XYZ. (there is good reason you never hear about node development milestones all that often, it is staid and boring when done right, and only interesting when crisis management is involved because the engineering is fubared at that company)

So what does all that jibber-jabber mean and why should you (cbn) care?

Because you (cbn, and the royal you) need to understand that everything to do with anything litho related (be it immersion vs EUV crossover, mask set count, min pitch geometry at any given node, etc.) is all about management picking a target cost structure that they are willing to accept on the basis of there being a spectrum of costs incurred and they know there is a range of acceptable costs for which they are prepared to absorb along any given key decision.

Do you need 10 wph or 60 wph for EUV to be "viable"? Completely depends on the cost structure that management is willing to absorb in their fiscal planning. You'll be guided to believe it is a specific hard number, that it is make or break for the technology if they can't get above an arbitrary throughput number or an equally arbitrary defectivity value.

But truthfully there is a LOT of wiggle room in there when it comes to the rubber meeting the road.

 

[cbn]

Because you (cbn, and the royal you) need to understand that everything to do with anything litho related (be it immersion vs EUV crossover, mask set count, min pitch geometry at any given node, etc.) is all about management picking a target cost structure that they are willing to accept on the basis of there being a spectrum of costs incurred and they know there is a range of acceptable costs for which they are prepared to absorb along any given key decision.

Do you need 10 wph or 60 wph for EUV to be "viable"? Completely depends on the cost structure that management is willing to absorb in their fiscal planning. You'll be guided to believe it is a specific hard number, that it is make or break for the technology if they can't get above an arbitrary throughput number or an equally arbitrary defectivity value.

But truthfully there is a LOT of wiggle room in there when it comes to the rubber meeting the road.

Regarding that cost structure that management is willing to absorb in their fiscal planning, it is very interesting to think about the various possibilities of that in the realm of consumer electronics.

So in a situation where management is willing to absorb higher costs, maybe we see EUV beginning to find its niche vs. 193nm immersion depending on various factors?

Maybe one of them is a die configuration (of a certain larger size) that does not lend itself well to die harvesting?

So maybe EUV isn't a good match for production of GPUs (just as one example) compared to 193nm immersion, but maybe at some point if it would work so much better for a fairly large die layout of different sort?

Then maybe after EUV finds this initial production niche, the EUV equipment development begins to pick up at a faster rate.

 

[witeken]

I don't think it will find niches because if you're gonna use EUV, it will be in multibillion USD fabs.

 

[Ajay]

Then maybe after EUV finds this initial production niche, the EUV equipment development begins to pick up at a faster rate.

A lot of money has been poured into EUV and still it's development is slow. It's just a very complex system. I don't envy the guys working on this problem.

Rather than prattle on, here's some background: http://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography
And some recent results: http://www.eetimes.com/document.asp?doc_id=1321162

 

[cbn]

I don't think it will find niches because if you're gonna use EUV, it will be in multibillion USD fabs.

.....So to clarify my earlier post:

Maybe for certain fab customers, with a large enough die size of mostly heterogeneous layout, at a certain high enough volume EUV (at X point in its early production development) will be a better choice than 193nm immersion lithography for the type of products that need to be made.

Then if EUV development improves much faster than the continued development for 193nm immersion, we see other types of chips move over to EUV as well.

So my point overall is that maybe the green light for EUV in production usage turns out not to be a simple "on and off" switch for fab wide general usage. Maybe the key for the involved parties of EUV is to find a niche chip production usage first.

Or maybe EUV just completely fails (and 193nm immersion is always the better choice even in the most extreme of circumstances). That could happen too.

 

[aigomorla]

18 to 24 months ahead... yeah right..

id say more like 30 to 36 month at the very least....
Intel is so far ahead of everyone, that they purposely lag themselves and wait on things because no one pulls out their last card til you've called the hand dealt on the cards.

I bet you they had 7nm way before even IDF announced it.
It was probably wrapped under so much NDA's internally, that it finally got approval to admit 7nm was doable now.

Just look at ES samples sent to respected partners of intel.
(i should know my sponsor when i was active was a trusted partner of intel)
They get the cpu's at least 1.5yrs in ADVANCE of what the consumer / enterprise sector get.

Yes 1.5yrs!
That's how far advance intel is.

 

[Fjodor2001]

I think the most interesting question is what 10, 7 & 5 nm will bring? Is it likely we'll see further frequency increases and/or lower power consumption? Or will it mainly increase transistor density?

If frequency cannot be increased much further despite the node shrinks, performance will not increase much either except from what can be gained by adding more CPU cores due to increased transistor density.

 

[witeken]

I think the most interesting question is what 10,

10nm will be the first node with post-silicon materials: SiGe, Ge or III-V. About a 0.5x shrink.

7

7nm could introduce an even better post-silicon material (III-V if Ge was used at 10nm) or an updated III-V FinFET like 2nd gen Tri-Gate is an update of 22nm.

It will also move to EUV & 450mm.

& 5 nm will bring?

5nm could see a move away from Tri-Gate with something like GAA or if both 10 and 7nm used Ge, will move to III-V. It could also introduce carbon nanotubes.

Is it likely we'll see further frequency increases and/or lower power consumption? Or will it mainly increase transistor density?

There could be some very major power consumption improvements. I'm not sure about frequency, but there's a reasonable chance some of reaching at least 6-8GHz.

 

[Fjodor2001]

There could be some very major power consumption improvements. I'm not sure about frequency, but there's a reasonable chance some of reaching at least 6-8GHz.

At what node? 10, 7, 5 nm or beyond?

Also, what would drive such frequency increases on those nodes, because lately we've not seen much frequency increase from node shrinks unfortunately.

 

[positivedoppler]

Mark Bohr is full of shit.
http://www.eetimes.com/author.asp?section_id=36&doc_id=1266087

 

[Idontcare]

Mark Bohr is full of shit.
http://www.eetimes.com/author.asp?section_id=36&doc_id=1266087

What is your point? Are you trying to say that just because he was wrong about the foundries at 20nm that must mean he also has no idea what he is doing at Intel in regards to Intel's advanced node development?

Really have no idea why your personal animosity towards Mark Bohr is being interjected into this thread. It seems entirely misplaced and irrelevant to the thread title.

 

[positivedoppler]

What is your point? Are you trying to say that just because he was wrong about the foundries at 20nm that must mean he also has no idea what he is doing at Intel in regards to Intel's advanced node development?

Really have no idea why your personal animosity towards Mark Bohr is being interjected into this thread. It seems entirely misplaced and irrelevant to the thread title.

I have no animosity towards him. Think I do throw that "full of shit" phrase out a lot perhaps in daily speech a bit too much. Usually in a playful manner with friends. The idea I was trying to get across is Mark Bohr can be overconfident in his claim and he has been wrong before.

 

[Idontcare]

I have no animosity towards him. Think I do throw that "full of shit" phrase out a lot perhaps in daily speech a bit too much. Usually in a playful manner with friends. The idea I was trying to get across is Mark Bohr can be overconfident in his claim and he has been wrong before.

Fair enough.

But I don't think he was overconfident in his statements regarding the 20nm foundry situation back in 2012 given that at that time it was the foundries who were telling their own customers to expect 20nm to cost more per xtor than 28nm.

What other conclusion was Mark Bohr supposed to draw from such statements? That they were lying and misrepresenting the business situation 2 years in advance just to convince Intel (and the foundry's customers) that the foundry model was on the edge of collapsing come 20nm?

I'm really not sure what alternative opinion Mark was supposed to have regarding the foundries and 20nm back in 2012. He either had to take them at face value, or prove they were lying and sandbagging their own projected cost curves. One of those two options is a fools-errand.

Can't blame him for reading into the foundry economics exactly what the foundry's were telling their own customers to read into them. (that prices/xtor were going up, not down, starting with 20nm and no reversal of that new trend would be in sight)

 

[Abwx]

Can't blame him for reading into the foundry economics exactly what the foundry's were telling their own customers to read into them. (that prices/xtor were going up, not down, starting with 20nm and no reversal of that new trend would be in sight)

The foundries economics says that none produce its own manufacturing tools and that none has a material advantage, it all boils down to their RD teams creativity and in this respect this guy assumed that only his crew had the capability to produce a valuable transistor geometry, that s quite a bold assumption, isnt it.?.

 

[positivedoppler]

I think 20 nm does cost more but Mark was claiming that the fabless model is dead and today the opposite is true. In the Article Bor was quoted like a PR machine, but that's his job working for Intel.

Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure.

That is a lot of extrapolating one flavor of 20nm = failure of fab process. I'm just going to quote the bottom of the article

"I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments."

Bohr does what he is paid for, and that is be Intel's PR. Two years ago he said " Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners."

Maybe Bohr knew back then that Intel might be competing against the other Fabs for business but given that Intel is now, we should take everything he says with a grain of salt. After all, it's his job to shake customer's faith in other Fabs and advertise Intel's. Some people are treating anything Bor says as gospel.

 

[Abwx]

That is a lot of extrapolating one flavor of 20nm = failure of fab process. I'm just going to quote the bottom of the article

TSMC is not operating in the same business, they need very low cost process, they had high perfs 20nm finfets designs since 2010 but who would pay 5000-6000$/waffer for cell phones SoCs dies.?.

Page 45 :
http://www.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse

 

[jdubs03]

This was posted today on the environment for EUV, pretty interesting to read, also essentially saying that Intel isn't confident in EUV for 7nm but rather 5nm.

http://www.eetimes.com/document.asp?doc_id=1323937&print=yes

 

[witeken]

Mark Bohr is full of shit.
http://www.eetimes.com/author.asp?section_id=36&doc_id=1266087

The foundry model is collapsing; he's right. The only question that remains to be answered is whether Intel's 2-year cadence is collapsing as well. We'll have more clarity on that when Intel launches 10nm, at which point we can start counting the years until TSMC offers something similar, which would be about half a decade. It doesn't even look good for TSMC's 2nd gen Tri-Gates, which will come 3+ years after Intel.

 

[witeken]

I think 20 nm does cost more but Mark was claiming that the fabless model is dead and today the opposite is true. In the Article Bor was quoted like a PR machine, but that's his job working for Intel.

Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure.

That is a lot of extrapolating one flavor of 20nm = failure of fab process. I'm just going to quote the bottom of the article

"I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments."

Bohr does what he is paid for, and that is be Intel's PR. Two years ago he said " Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners."

Maybe Bohr knew back then that Intel might be competing against the other Fabs for business but given that Intel is now, we should take everything he says with a grain of salt. After all, it's his job to shake customer's faith in other Fabs and advertise Intel's. Some people are treating anything Bor says as gospel.

You have no idea.

Mark T. Bohr is an Intel Senior Fellow and director of Process Architecture and Integration at Intel Corporation. He is a member of Intel's Logic Technology Development group located in Hillsboro, Oregon, where he is responsible for directing process development activities for Intel's advanced logic technologies. He joined Intel in 1978 and has been responsible for process integration and device design on a variety of process technologies for memory and microprocessor products. He is currently directing development activities for Intel's 10 nm logic technology. Bohr is a Fellow of the Institute of Electrical and Electronics Engineers and was the recipient of the 2012 IEEE Jun-ichi Nishizawa Medal and 2003 IEEE Andrew S. Grove award. In 2005 he was elected to the National Academy of Engineering. He holds 73 patents in the area of integrated circuit processing and has authored or co-authored 49 published papers.

 

[Idontcare]

The foundry model is collapsing; he's right. The only question that remains to be answered is whether Intel's 2-year cadence is collapsing as well. We'll have more clarity on that when Intel launches 10nm, at which point we can start counting the years until TSMC offers something similar, which would be about half a decade. It doesn't even look good for TSMC's 2nd gen Tri-Gates, which will come 3+ years after Intel.

Too early to call that IMO given that the foundry TAM only continues to grow year after year.

The foundry model may be sucking more and more for the fabless customers who depend on it, but they are still willing to pay and be customers of it as evidenced by foundry TAM results.

What Intel doesn't tell us is how their wafer costs compare to TSMC's. They may have the highest performing stuff on the planet, but at what cost?

Sure Intel's own products and margins cover their fabbing expenses, but could an Nvidia afford to produce its GPUs at Intel as a foundry any more than they can afford to have them produced at TSMC?

 

[positivedoppler]

You have no idea.

I am aware of his very impressive resume, but I still reserve the right to be very sceptical of his very pro Intel and probably heavily coached by PR filtered output. He has a stake in Intel. Intel is now competing in the foundry business. So he claims all other foundries are collapsing. Only Intel has what it takes. EUV wont be available until 5 nm. Fear not Intel can do 7 nm without EUV. This is really great pr and business ad for Intel if you were to believe all of it.

 

[witeken]

He was just answering a question.

“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.