Mark Bohr: Intel can do 7nm without EUV

[Phynaz]

“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.

Of course no details given.

Further in the article -

“One thing they don’t talk about is parametric yields,” said Handel Jones, principal of International Business Strategies. “It took them 18 months to address that” at the 14 nm node.

However, Jones added, “We still think they have an 18- to 24-month lead on other foundries in terms of manufacturing high volumes with reductions in cost per transistor.”

http://www.eetimes.com/document.asp?doc_id=1323865&page_number=1

 

[videogames101]

Of course there is a way, there's always a way - but it's not always cost effective. If you want a 7nm chip, we can make one wafer at a time starting tomorrow, but you can't make money doing that.

 

[cbn]

Thanks for the article.

It will be interesting to see what Intel targets for die sizes on 10nm and beyond.

How much smaller will the average die size be?

Obviously, if new xtor designs (Tunnel FETs, etc.) have good merit for purposes of improved drive current/leakage these advanced nodes will be much in demand. But then how much would smaller average die sizes impact the other aspects of chip design......

 

[Phynaz]

Of course there is a way, there's always a way - but it's not always cost effective. If you want a 7nm chip, we can make one wafer at a time starting tomorrow, but you can't make money doing that.

Didn't read the article, did you?

 

[Khato]

Thanks for the link, really makes me wish that Intel actually webcast some of the technical sessions. The fact that Intel is using triple patterning "on one or more critical layers" is certainly an interesting tidbit.

 

[witeken]

7nm should be a very interesting node indeed. EUV, 450mm, III-V. Very interesting to hear what's possible with light wave lengths that are literally an order of magnitude bigger than the transistors, but the ~quintuple patterning that would be necessary will be really expensive if ASML doesn't get its EUV machines up to snuff.

 

[frozentundra123456]

Well considering the problems with 14nm, I would take this with a grain of salt. Also, as others said, it is not only being able to do it, but how many more die shrinks will be cost effective, both from a price per transistor cost and how much performance improvement there is.

 

[Arachnotronic]

Thanks for the link, really makes me wish that Intel actually webcast some of the technical sessions. The fact that Intel is using triple patterning "on one or more critical layers" is certainly an interesting tidbit.

They eventually post webcasts. Wait a week or two.

 

[witeken]

Well considering the problems with 14nm, I would take this with a grain of salt.

Without knowing the specifics about their 14nm yield problems, you can't comment on the yields for future nodes that won't use EUV, like 10nm.

Also, as others said, it is not only being able to do it, but how many more die shrinks will be cost effective, both from a price per transistor cost and how much performance improvement there is.

I really wouldn't worry about price per transistor, 7nm will very likely use EUV. Performance and power actually get worse every die shrink, due to quantum tunneling, but that is partly compensated by better technologies.

 

[cbn]

Two interesting things to think about IMO, if average die sizes become much smaller on advanced nodes:

1. The value of interconnecting smaller dies together in some way.

2. The value of the Rockchip Alliance (maybe making some die configurations we are not normally used to seeing would help the node ramp up faster)

 

[videogames101]

Didn't read the article, did you?

nope

 

[meloz]

If Mr. Bohr's day job is working on 7nm, I take that as evidence that 10nm is cleared for takeoff. Cannonlake @ 10 nm coming in 2016, get hyped.

Intel's manufacturing lead is just sickening.

 

[Idontcare]

If Mr. Bohr's day job is working on 7nm, I take that as evidence that 10nm is cleared for takeoff. Cannonlake @ 10 nm coming in 2016, get hyped.

Intel's manuafcturing lead is just sickening.

Oh yeah, at this stage in 10nm development (with respect to the timeline for ramping to production) they should be well past dialing in the parametric targets (hitting drive currents and voltage specs) and beginning the work on engineering the reliability so the chips can last 10yrs instead of 2 weeks.

 

[Homeles]

So what would they use, EBL? I can't imagine octa-patterning being very economical...

 

[Ajay]

So what would they use, EBL? I can't imagine octa-patterning being very economical...

Neither is EBL, at least right now.

 

[cbn]

Although wafer costs rose at an accelerating rate for the last two nodes due to the need for more masks, Intel continues to pack more transistors in a given area of silicon. The density offsets wafer costs, leading to the cost-per-transistor decline, Bohr said in his talk on Intel’s 14 nm process.

With the importance of density for cost savings emphasized....

....For the most extreme budget desktop chips, I have to wonder if designing a processor with a single big core (and enabling almost every feature like hyperthreading, AVX,etc.) would be more economical than taking a dual big core die and disabling many features (AVX, hyperthreading, cache) to make a bargain desktop chip?

I'm thinking maybe a 1C/2T 16 EU processor (with fast clocks) to replace not only the most bargain dual big core desktop chips, but Braswell as well. Definitely Braswell replaced for desktop. (1 big core with hyperthreading at full speed >> four small atom cores IMO)

Not only that but starting off with a smaller die would help yields from defects as well. ( A die with only one big core is a smaller die than one with two big cores)

 

[Idontcare]

So what would they use, EBL? I can't imagine octa-patterning being very economical...

Octa-patterning would not be economically viable if you had to do it at every level, but adding a few more masks to an already large mask-count device is merely an incremental cost adder.

Nobody wants incremental cost-adders, which is why the topic receives as much press as it does, but it is also not the untenable demon that it gets made out to be.

EBL is enabling for foundries because a considerable percentage of their customers are doing small volume products which are not economically viable with advanced node mask set costs.

If a customer has an existing product currently fabbed at 65nm, and maybe asks TSMC to churn out 20 lots (20 lots x 24 wafers/lot = 480 wafers) per business quarter, that customer is never going to migrate their 65nm design to 28nm or 20nm or 16FF+, etc because the mask costs alone would dwarf the revenue despite the likelihood of the shrunken chips enabling higher ASP owing to improved electrical performance.

However, if TSMC (or any other foundry) can offer the low-volume lagging node customers a mask-less option for advanced nodes, there are a LOT of customers who would jump at the opportunity.

The following dataset are a bit dated by now, but this is actual data from TSMC regarding their customer's volume mix on a lagging node:

What these data show is that (at the time) nearly 45% of the wafers in their fabs were for customers who only wanted 1 or 2 lots (24 wfrs per lot) of production in the fab.

If you can fully digest the totality of that distinction then you'll come to understand why TSMC is the lead proponent in pushing EBL towards production readiness.

 

[witeken]

If Mr. Bohr's day job is working on 7nm, I take that as evidence that 10nm is cleared for takeoff. Cannonlake @ 10 nm coming in 2016, get hyped.

Intel's manufacturing lead is just sickening.

No surprises there:

Intel: We know how to make 10nm chips (IDF 2012)

 

[ShintaiDK]

It makes me wonder if EUV will ever take off. Its been the golden grail in terms of cost reduction for many years now. But constantly failed to materialize.

 

[witeken]

It makes me wonder if EUV will ever take off. Its been the golden grail in terms of cost reduction for many years now. But constantly failed to materialize.

EUV works, but not for HVM yet. The throughput is gradually increasing, but still not enough (until ~2016).

 

[ShintaiDK]

EUV works, but not for HVM yet. The throughput is gradually increasing, but still not enough (until ~2016).

If Intel talks about no EUV for 7nm. Then its unlikely we see EUV the next 5 years.

 

[witeken]

If Intel talks about no EUV for 7nm. Then its unlikely we see EUV the next 5 years.

You have to look at it from this context:

"I'd like to have EUV for 10, but I can't bet that it would be ready in time," Bohr said, hinting at the difficulties in using this method. EUV has much higher costs than immersion lithography.

There's a >90% chance that Intel will use EUV at 7nm, but if ASML fails for some reason, they have to have an alternative, else there will be big delays. So it a good sign that Intel is also able to manufacture 7nm chips without EUV.

 

[videogames101]

Octa-patterning would not be economically viable if you had to do it at every level, but adding a few more masks to an already large mask-count device is merely an incremental cost adder.

Nobody wants incremental cost-adders, which is why the topic receives as much press as it does, but it is also not the untenable demon that it gets made out to be.

EBL is enabling for foundries because a considerable percentage of their customers are doing small volume products which are not economically viable with advanced node mask set costs.

If a customer has an existing product currently fabbed at 65nm, and maybe asks TSMC to churn out 20 lots (20 lots x 24 wafers/lot = 480 wafers) per business quarter, that customer is never going to migrate their 65nm design to 28nm or 20nm or 16FF+, etc because the mask costs alone would dwarf the revenue despite the likelihood of the shrunken chips enabling higher ASP owing to improved electrical performance.

However, if TSMC (or any other foundry) can offer the low-volume lagging node customers a mask-less option for advanced nodes, there are a LOT of customers who would jump at the opportunity.

The following dataset are a bit dated by now, but this is actual data from TSMC regarding their customer's volume mix on a lagging node:

What these data show is that (at the time) nearly 45% of the wafers in their fabs were for customers who only wanted 1 or 2 lots (24 wfrs per lot) of production in the fab.

If you can fully digest the totality of that distinction then you'll come to understand why TSMC is the lead proponent in pushing EBL towards production readiness.

I wouldn't want to be the guy designing cells for octa-patterning rule-decks.

 

[Ajay]

What these data show is that (at the time) nearly 45% of the wafers in their fabs were for customers who only wanted 1 or 2 lots (24 wfrs per lot) of production in the fab.

If you can fully digest the totality of that distinction then you'll come to understand why TSMC is the lead proponent in pushing EBL towards production readiness.

Thanks IDC. I had read, last year, that allot of effort was being put into EBL and MBE. That seemed sensible until I learned about the many challenges facing both technologies. However, the data you provided shows that one problem, longer wafer processing times, is less of an issue due to the short runs required to fulfill customer orders.

 

[cbn]

It makes me wonder if EUV will ever take off. Its been the golden grail in terms of cost reduction for many years now. But constantly failed to materialize.

I've been wondering that myself.....and what types of chips benefit the most from EUV compared to 193nm immersion.

Since I have to imagine EUV (at the beginning stages of HVM adoption) reduces defects at the expense of throughput: Maybe a processor with a high amount of heterogeneity (like an SOC) is a better choice for application of EUV at critical layers than a CPU or GPU with a lot of repeated units (ie, a chip that can more easily be binned if one or more defects occur).

Does that logic follow?