Info LPDDR6 @ Q3-2025: Mother of All CPU Upgrades

[Io Magnesso]

JEDEC® Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance | JEDEC

www.jedec.org

Yep, about time: Right before year-end launching of important SoC.



So far, we know 8 Elite G2 and X Elite G2 are going to support LPDDR6. Both SoC are using same Oryon v3 cores, GB6 ST should surpass 4000+. X Elite G2 would be in range of upcoming Apple's M5 Pro.



Still not sure Dimensity 9500 with X935 cores would support LPDDR6 or not, we shall see...

No signs of iPhone SoC would employ LPDDR6. But man, I would bet M5 series are going full throttle support of 96-bit, 192-bit and 384-bit LPDDR6.

NV's GB10 might as well, we shall see. In case of supporting LPDDR6, GB10 would be in range of M5 Max, not Pro level.

From previous generation GB6 scores below 3000 average... (oryon v1)
The expectation that it suddenly jumps higher than 4000 score is a dream story.

 

[Tigerick]

Qualcomm Technologies, Inc. is a global leader in AI edge innovation and is proud to be one of the first in the industry to implement LPDDR6

One of the first, interesting terms. Cause we know Qualcomm will announce both SoC in Qualcomm Summit in Sept 23. They should claim the first if no other vendors are announcing LPDDR6 support before Sept 23. Hmm, from now on until Sept 23, there are following events:

• NV GB10 launching this month
• Mediatek Dimensity 9500 may drop earlier in Sept

Two vendors which could potentially launch their SoC supporting LPDDR6. We shall hear more in the coming days...

 

[igor_kavinski]

The expectation that it suddenly jumps higher than 4000 score is a dream story.

I don't know. I wouldn't bet against Gerard Williams.

 

[poke01]

From previous generation GB6 scores below 3000 average... (oryon v1)
The expectation that it suddenly jumps higher than 4000 score is a dream story.

Qualcomms aim will be to beat M4 Max and for that they need to aim for >4000.

 

[igor_kavinski]

Qualcomms aim will be to beat M4 Max and for that they need to aim for >4000.

Probably only possible way outside of some serious miracle is a crazy good implementation of SME.

 

[Tuna-Fish]

Cadence announced yesterday that they taped out a combined LPDDR5/LPDDR6 controller.

Given how different the standards are, that's a weird product.

 

[igor_kavinski]

Given how different the standards are, that's a weird product.

Probably means that there's a lot of untapped LPDDR5 supply and it may not dry up for a couple years at least. Also, shifting complete production over to LPDDR6 isn't something they want to do with all of their fabs for cost reasons so probably gonna keep pumping out LPDDR5 for quite some time.

 

[Doug S]

Cadence announced yesterday that they taped out a combined LPDDR5/LPDDR6 controller.

Given how different the standards are, that's a weird product.

For OEMs who want to serve a wide range of products with a single SoC maybe that's not too crazy? Either because you want to operate at different price points (LPDDR6 is going to cost a lot more than LPDDR5/X for the first couple years) or you plan for a single product to live long enough that the supply of LPDDR5 might dry up before you replace it.

I'd really be curious to know how its size compares to the size of their LPDDR5 only and LPDDR6 only controllers in the same process. Maybe there is no area savings per se but if there are significant savings in shoreline that might be enough to justify this misfit toy.

 

[Cheesecake16]

JEDEC® Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance | JEDEC

www.jedec.org

Yep, about time: Right before year-end launching of important SoC.



So far, we know 8 Elite G2 and X Elite G2 are going to support LPDDR6. Both SoC are using same Oryon v3 cores, GB6 ST should surpass 4000+. X Elite G2 would be in range of upcoming Apple's M5 Pro.



Still not sure Dimensity 9500 with X935 cores would support LPDDR6 or not, we shall see...

No signs of iPhone SoC would employ LPDDR6. But man, I would bet M5 series are going full throttle support of 96-bit, 192-bit and 384-bit LPDDR6.

NV's GB10 might as well, we shall see. In case of supporting LPDDR6, GB10 would be in range of M5 Max, not Pro level.

1) GB10 is LPDDR5X-8533 not LPDDR6
2) I doubt that any SOC launching this year will have LPDDR6 because none of the memory manufacturers have announced LPDDR6 high volume production and the JEDEC announcement doesn't actually say that 8 Elite G2 or X Elite G2 will have LPDDR6... Perhaps it uses LPDDR5X/LPDDR6 but launches with LPDDR5X to start with...

 

[Doug S]

So wccftech posted an article about DDR6 which appears to repeating something I've posted here and RWT. They said DDR6 would have four 24 bit channels, a claim I've never seen anywhere but my own posts. The DDR6 spec still hasn't been released so there's nothing official, so either they have some insider info or more likely they got that from me.

I've posted my reasoning why I think that before, but that's not the only way to do it. JEDEC could do it the "obvious but wasteful" way, making standard DDR6 four 16 bit channels and ECC DDR6 four 16+8 bit channels, a full 50% bit overhead for ECC. While wasteful it has the virtue of simplicity and doing things the same way past DDR standards have. Another possibility would be increasing the burst length. LPDDR6 bumped its burst length to 24 to make the math work with its 12 bit channels, so if DDR6 wanted to stick with 16 bit channels, a burst length of 18 ends up with the same 288 bits as LPDDR6.

Anyway, I think it would be funny if they are so confidently repeating what I said, since I'm just speculating and could easily be wrong.

https://wccftech.com/ddr6-memory-de...window-with-8800-mtps-base-17600-mtps-speeds/

 

[NTMBK]

So wccftech posted an article about DDR6 which appears to repeating something I've posted here and RWT. They said DDR6 would have four 24 bit channels, a claim I've never seen anywhere but my own posts. The DDR6 spec still hasn't been released so there's nothing official, so either they have some insider info or more likely they got that from me.

I've posted my reasoning why I think that before, but that's not the only way to do it. JEDEC could do it the "obvious but wasteful" way, making standard DDR6 four 16 bit channels and ECC DDR6 four 16+8 bit channels, a full 50% bit overhead for ECC. While wasteful it has the virtue of simplicity and doing things the same way past DDR standards have. Another possibility would be increasing the burst length. LPDDR6 bumped its burst length to 24 to make the math work with its 12 bit channels, so if DDR6 wanted to stick with 16 bit channels, a burst length of 18 ends up with the same 288 bits as LPDDR6.

Anyway, I think it would be funny if they are so confidently repeating what I said, since I'm just speculating and could easily be wrong.

https://wccftech.com/ddr6-memory-de...window-with-8800-mtps-base-17600-mtps-speeds/

I would not be surprised if an LLM was trained on your forum posts and is now confidently regurgitating your speculation as facts.

 

[Tigerick]

	AMD AI 9 HX375 Strix Point	Medusa Halo Mini		Nova Lake - H		AMD AIMax+ 395 Strix Halo	Medusa Halo	RTX 5070 Super
TDP	28 W	?		?		55W	?	275 W
Total Dies	1	2		5 + Base		3	3	1
CPU	4 x Zen5 + 8 x Zen5c	4 x Zen6 + 8 x Zen6c		4 + 8		16 x Zen 5	24 x Zen 6
Threads	24	24		12		32	48
Node	4nm N4P	N3P		N2		4nm N4P	N3P
Max Boost Clock	5.1 GHz	?		?		5.1 GHz	?
GPU + IOD	Radeon 890M	RDNA5 Model AT4		Arc Model ?		Radeon 8060S	RDNA5 Model AT3	GB205
Node	iGPU	N3P / X		N3E		4nm N4X	N3P / X	4N
CU / SM /Xe	16	24		12		40	48	50
IC	NA	10 MB				32 MB	20 MB	48 MB
Memory Interface	128-bit LPDRR5x-8000	192-bit LPDDR6		128-bit LPDDR5x-8533 ?		256-bit LPDRR5x-8000	384-bit LPDDR6	192-bit GDDR7
Max Memory	256 GB	256 GB ?		?		128 GB	512 GB ?	18 GB
Memory BW	128 GB/s	307 GB/s		136 GB/s		256 GB/s	614 GB/s	672 GB/s
NPU	55 TOPS	>= 70 TOPS		>= 70 TOPS		50 TOPS	>= 70 TOPS

Geez, MLID has updated Medusa Halo specs with non-sense about AT3 and AT4. They are not designed as discreet GPU just like Radeon 8060S is not used as discreet GPU. Too damn stupid for me to explain, please refer to the table above with my understanding below:

• LPDDR6 should be standard by 2027. Thus, I am focusing on LPDDR6.
• Medusa Halo no doubt is going to be flagship CPU+GPU SoC with 24-core Zen 6 and 48CU RDNA5. But AMD won't be the leader anymore. I will update the table with N1X and Qualcomm X Elite G2 which are shipping by the end of this year.
• Medusa Halo Mini or used to call Medusa Little Halo is more like Strix Point successor with 4+8+2 CPU and 24 CU RDNA5. If you are disappointed by STX's GPU performance, then wait for Medusa Halo Mini. Mini no longer remains monolithics design though; AMD has to split the SoC to 2 dies.
• I have included the upcoming Intel Nova Lake-H SoC. If you guys want to know more about the changes in tile design, please refer to main page of Nova Lake Discussion. Why comparing to NVL, not PTL? Well, 18A is so broken that Intel could not ship full die of PTL, that is 4+8+4 core configuration. Intel has to use the cut die of N2 8+16 to create 4+8+4 die. Initially, SoC that are made by 18A supposedly to include iGPU; it seems that part is canned thus Intel has to use tGPU to combine as one SoC. That's mean total dies of Mobile Nova Lake is 5 dies excluding base tile. That's why I said PTL-H and NVL-H are both DoA & that's why Pat are fired, so much for 5NI4Y.

 

[igor_kavinski]

https://www.ntchip.com/electronics-news/lpddrx-memory-guide

Interesting bit for me:

LPDDR6 uses a complex dual sub-channel architecture, where each die's 24-bit channel is split into two 12-bit sub-channels. This design shortens access paths, significantly reducing latency.

So hopefully, we will be rid of the curse of 100+ ns latencies?

 

[Doug S]

https://www.ntchip.com/electronics-news/lpddrx-memory-guide

Interesting bit for me:



So hopefully, we will be rid of the curse of 100+ ns latencies?

I'm not sure what they're smoking, but that isn't going to make any real difference. The main reason for longer latencies for LPDDR is that it is designed for low power, so it uses lower drive currents and lower capacitance connections between controller and chips. LPDDR5 already supported half width channel operation, so if that could deliver significant latency improvements someone would have already been doing it.

Since almost all of the overall DRAM power is consumed by the controller/interface not actual reading and writing of bits (~99% for DDR5 controllers) any power savings have to be won on the controller side. Whatever changes you make to the controller and the protocol it uses to reduce its power needs have to be paid for in some manner - and latency is how you pay.

 

[Darkmont]

https://www.ntchip.com/electronics-news/lpddrx-memory-guide

Interesting bit for me:



So hopefully, we will be rid of the curse of 100+ ns latencies?

This happened with DDR5 and helps with lower latency under load not AIDA cope latencies. LPDDR has had sub-channels since LPDDR4, not new.

 

[Tuna-Fish]

I don't understand how the sub-channel architecture is supposed to reduce latency?

It is a nice power optimization for low-load situations. When the load is low, you can turn off half of your bus and do transfers with twice the burst length instead. This increases latency (by like 2ns, not that it matters).

 

[Darkmont]

I don't understand how the sub-channel architecture is supposed to reduce latency?

It is a nice power optimization for low-load situations. When the load is low, you can turn off half of your bus and do transfers with twice the burst length instead. This increases latency (by like 2ns, not that it matters).

Splitting channels allows both to serve accesses independently. Timings are independent between subchannels. Going from a 64-bit channel and 8n prefetch to a 32-bit channel and 16n prefetch means that two channels in say a DIMM or module can service a 64-byte cache line vs one.

 

[Doug S]

Splitting channels allows both to serve accesses independently. Timings are independent between subchannels. Going from a 64-bit channel and 8n prefetch to a 32-bit channel and 16n prefetch means that two channels in say a DIMM or module can service a 64-byte cache line vs one.

Doubling up on subchannels to able to service twice as many independent cache line refills makes for a good fit for modern CPUs that have more and more cores all doing their own thing. Hence DDR5 getting two subchannels, and DDR6 going to four.

But it sounds like @igor_kavinski wants to see DRAM load to use latency go down (that's where his 100ns comes from) but adding subchannels won't help that anymore than adding more full channels will.

 

[igor_kavinski]

But it sounds like @igor_kavinski wants to see DRAM load to use latency go down (that's where his 100ns comes from) but adding subchannels won't help that anymore than adding more full channels will.

Page 3 - Question - Post your MaxxMem² score

Page 3 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

If it's possible to reduce the latency and improve responsiveness AND performance on LPDDR4, I don't see why things can't improve on LPDDR6.

 

[Darkmont]

Page 3 - Question - Post your MaxxMem² score

Page 3 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

If it's possible to reduce the latency and improve responsiveness AND performance on LPDDR4, I don't see why things can't improve on LPDDR6.

The internals have already reached their respective bandwidth-latency-area-power tradeoffs for what LPDDR’s market segments are.

 

[mikk]

Initially, SoC that are made by 18A supposedly to include iGPU; it seems that part is canned thus Intel has to use tGPU to combine as one SoC. That's mean total dies of Mobile Nova Lake is 5 dies excluding base tile. That's why I said PTL-H and NVL-H are both DoA & that's why Pat are fired, so much for 5NI4Y.
[/LIST]

Are you sure? Raichu told iGPU part IS based on 18A(P) family two days ago.

 

[marees]

They are not designed as discreet GPU just like Radeon 8060S is not used as discreet GPU. Too damn stupid for me to explain, please refer to the table above

I didn't follow this. Why can't AT3 & AT4 be stand alone GPU dies ?