Info LPDDR6 @ Q3-2025: Mother of All CPU Upgrades

[inquiss]

Zen7 on AM5?

No, I think kepler means that zen 7 is 5 years away /s

 

[Doug S]

You are still getting a third more B/W at the same frequencies.
For eg. standard dual channel LPDDR5X @10667MT/s will get ~170GB/s,
standard dual channel LPDDR6 @10667MT/s will get ~227.5GB/s.

But yeah LPDDR6 is still quite some time away for being available and then become mainstream. DDR6 seems even further away for availability .

That's because an LPDDR6 controller is 24 bits wide instead of LPDDR5X's 16, meaning a LPDDR6 controller will be physically larger and require more shoreline and pins. If you devote more area/shoreline/pins to LPDDR5X you can get more bandwidth too. LPDDR5X-10666 actually offers slightly more bandwidth than LPDDR6-10666 (assuming the same total width of memory bus) due to LPDDR6's extra bits for ECC/tagging.

 

[johnsonwax]

Zen7 on AM5?

You should open a Zen7 Speculation Thread.

 

[marees]

You should open a Zen7 Speculation Thread.

Here is the zen 7 SPECULATION thread

1.4nm
33 cores ccd
264 core processor

AMD's next-gen Zen 7 chips with X3D teased, new 3D cores, and more in fresh rumors
AMD's future-gen Zen 7 CPU architecture rumored with '3D cores' that would usher in 'absurdly high' performance increases for gaming.

Read more: https://www.tweaktown.com/news/1052...-3d-cores-and-more-in-fresh-rumors/index.html

AMD Zen 7 will pull further ahead of Intel with dedicated 3D core, says leak

Though its release is still far in the future, veteran hardware leaker MLID says Zen 7 CPUs could vastly improve performance with 3D cores.

www.pcguide.com

AM5 ??

https://twitter.com/x/status/1956125577271730369

 

[regen1]

That's because an LPDDR6 controller is 24 bits wide instead of LPDDR5X's 16, meaning a LPDDR6 controller will be physically larger and require more shoreline and pins. If you devote more area/shoreline/pins to LPDDR5X you can get more bandwidth too. LPDDR5X-10666 actually offers slightly more bandwidth than LPDDR6-10666 (assuming the same total width of memory bus) due to LPDDR6's extra bits for ECC/tagging.

Yeah that part is known but does it matter much that frequency alone doesn't move much initially when we can get B/W gain from increased width and subsequently gain with frequency improvements that follow?

For the last few years we mostly got improvements of 1066MT/s in LPDDR5X(improvement cadence)
Let's take a mainstream platform. For eg.
MTL-H(7467MT/s)--> Lunar Lake/ARL-H(8533MT/s)-->PTL-H(9600MT/s)
In a Dual-channel config we have been getting ~17GB/s per gen(cadence).
Let's say hypothetically with NVL-H we get LPDDR5x 10667MT/s(another same bump) but in 2028 we get even the base specs LPDDR6(10667MT/s), we are still getting a lot (~57GBps in Dual channel or one-third B/W gain over previous gen). That's still a fairly decent gain while moving to new standard and then subsequent gains follow from increased frequencies.

 

[johnsonwax]

Here is the zen 7 SPECULATION thread

Oh, you should start a Zen 8 Speculation Thread then. 7GHz?

 

[NTMBK]

Oh, you should start a Zen 8 Speculation Thread then. 7GHz?

sigh I'm ready to say the line

 

[Doug S]

Yeah that part is known but does it matter much that frequency alone doesn't move much initially when we can get B/W gain from increased width and subsequently gain with frequency improvements that follow?

For the last few years we mostly got improvements of 1066MT/s in LPDDR5X(improvement cadence)
Let's take a mainstream platform. For eg.
MTL-H(7467MT/s)--> Lunar Lake/ARL-H(8533MT/s)-->PTL-H(9600MT/s)
In a Dual-channel config we have been getting ~17GB/s per gen(cadence).
Let's say hypothetically with NVL-H we get LPDDR5x 10667MT/s(another same bump) but in 2028 we get even the base specs LPDDR6(10667MT/s), we are still getting a lot (~57GBps in Dual channel or one-third B/W gain over previous gen). That's still a fairly decent gain while moving to new standard and then subsequent gains follow from increased frequencies.

You seem to be relying on the information found in this graphic from the first post of this thread:

Do you not notice that jump from "x64" to "x96"? That is not free, and it something any OEM could choose to TODAY with LPDDR5X for roughly the same cost, and get MORE bandwidth than LPDDR6.

The ONLY advantages to LPDDR6-10666 are Samsung's reported 20% power savings, and the ability to use those extra bits for ECC or tagging. The disadvantage is that you get 114.1 GB/s, whereas LPDDR5X-10666 at the same x96 width would provide 128.4 GB/s. There's also the downside that LPDDR6 is going to cost a LOT more initially, and it will take probably two years before it is at price parity with LPDDR5X.

Smartphones today have 64 bit wide memory busses, with four LPDDR5X controllers. Do you really believe they are going to go to a 96 bit wide bus when they transition to LPDDR6, because "4" memory controllers is some kinda magic number? Most likely they'll go to 72, which would give them EXACTLY the same 85.6 GB/s that a 64 bit wide LPDDR5X bus provides.

Ditto with PCs, they aren't going to go from 128 bit to 192 bit simply because "8" memory controllers is a magic number.

 

[SteinFG]

Most likely they'll go to 72, which would give them EXACTLY the same 85.6 GB/s that a 64 bit wide LPDDR5X bus provides.

Yeah, phone makers will go for more expensive memory, in order to *checks notes* get no benefit whatsoever. brilliant!