Originally posted by: bryanW1995
while there certainly isn't any evidence about nehalem's ability to clock or lack thereof, it does seem likely that they'll have difficulty getting the same clocking ability. fortunately for intel, they had so much headroom on core2 that they might be able to SELL the chips at the same clockspeed, however. a 4 core monolithic die is much harder to ramp up to 3.0+ ghz than 2 duals slapped together, yields will be much better, etc. I'm not saying that they won't get there, I'm just saying that even if oc'ing ends up being kosher in mid/low end don't expect 50% + oc's this time around
I'd like to add some thoughts to this if I may.
Point 1: Consider that current Penryn speedbins (and Conroe) are not necessarily a representation of the distribution of clockspeeds coming out of the fabs.
Without competition pressuring higher speedbins we are most surely benefiting (as overclockers) from chips on the market having much more clocking headroom than they might otherwise have had were Phenom's hitting 3.8GHz right now.
So Nehalem may very well arrive with similiar "clocking margin" baked in simply because there is no need for a 4GHz Nehalem with a 140W TDP. It will be sold as a 3.2GHz 95W TDP part, and if folks bolt on water-cooling gear or a Tuniq120 and are willing to dissipate the 140W at 4GHz then you get to go for it.
Point 2: Clockspeed limitations due to clock propagation across a die (called clock domain skew) is a real phenomenon BUT it applies more to those designs where the logic across the entire die area needs to be synchronized. I.e. single-core chips.
A quad-core chip does not necessarily require the clockskew to be negligable relative to the overall IC's clock frequency. Core 1 being slightly skewed in clocks to Core 2 is not the end of the world provided the circuitry is present to recognize when and how shared memory accesses need to be checked against these kinds of things. Consider that AMD's Phenom can have core's clocked independently.
So Nehalem being a large die does not necessarily mean getting all four cores to clock at 4GHz is going to be any more or less challenging than getting four cores from two MCM'ed die to operate at 4GHz.
Being that all four cores are literally next to each other, the chances of having process induced variations within the die causing one core to be substantially inferior is not very likely. Back when 6-inch wafers were king then yes process variation across a 6" wafer would impact a 250mm^2 die, but now that 12-inch wafers are king it is just quite unlikely.
Point 3: Intel's issue with selling Nehalem versus Penryn is gross margins versus yield. The larger die will result in lower yields, this is an immutable boundary condition of manufacturing processes. The fab's defect density will cause larger dies to have lower yield than smaller dies, no way around it.
So fewer sellable chips per wafer (than Yorkfield) means the gross margins will be lower (than Yorkfield) unless the selling prices are higher (than Yorkfield).
Bloomfield will literally canabilize Intel's own gross margins on QX9650 and QX9770 while at the same time not necessarily bringing higher profits (unless they sell Bloomfield for $1500-$2000) but the gross margins will be lower (yields will be lower) unless they sell for higher ASPs.
This is Intel's issue, they must extract higher gross margins with Nehalem to justify replacing Penryn (on the desktop). If they don't then they are truly wasting their shareholder's entitled profits that could be garnered from selling more Penryn.
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