It's twofold ... the clock synthesizer PLL chip must be capable of producing output clocks at those ratios, and then the
system chipset must be able to cope.
Not all chipsets do it the same way. Traditionally, SiS chipsets can run completely asynchronously, so you can use a
PLL that outputs a constant 33 MHz clock for PCI regardless of the CPU and RAM clocks. VIA and Intel chipsets
do nothing but integral multiples (2/1, 3/1, 4/1, maybe 5/1 too), while some of ALi's also support running on
fractioned multiples (5/2 and such) but not real async.
Then there's AGP to add to the game ... the AGP clock is coming out of the chipset, and this is where the chipset has
to get it right for every thinkable CPU/RAM/PCI clock combination. (E.g. this is why Intel BX can't do 133 MHz CPU bus
right, because it can't do AGP=CPU/2.)
regards, Peter