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Llano power consumption better than we thought?

that's a bit better than the undervolt on my 630 (1.225). my idle is lower (.8750) but that's probably only a couple watts or so.
 
veri745 said:
Idle on Llano matters a lot less than on Athlon II, since it has power gating.
Click to expand...

true. even still, probably a couple watts or so. if i cut the volts by 33% to get a 3 or 4 watt decrease it wasn't pulling that much to begin with.
 
yeah i dont think idle is going to make a huge difference.

on my llano at stock everything, idle isl ike 30W but full prime 95 load is somethingl ike 131W from the wall on an 80plus bronze psu.

so at load it has actaully huge power consumption for a 32nm chip
 
hans007 said:
yeah i dont think idle is going to make a huge difference.

on my llano at stock everything, idle isl ike 30W but full prime 95 load is somethingl ike 131W from the wall on an 80plus bronze psu.

so at load it has actaully huge power consumption for a 32nm chip
Click to expand...

When I see first-hand reports like this it doesn't surprise me at all that bulldozer was delayed. They are probably wrestling with some serious power-consumption issues.
 
hans007 said:
yeah i dont think idle is going to make a huge difference.

on my llano at stock everything, idle isl ike 30W but full prime 95 load is somethingl ike 131W from the wall on an 80plus bronze psu.

so at load it has actaully huge power consumption for a 32nm chip
Click to expand...

Thats only about 110 (or less) actual watts being consumed by components other than the power supply. Subract everything except the motherboard and you're probably looking at 80 watts right? Now subtract the 10-15 watts the south bridge and other chips use and you get 70 watts, at most. Now subtract the amount of power the DDR3 chips consume. Is that 3-5 watts per dimm? So lets be conservative and say that leaves us with 65 watts for the cpu at full load. Now subtract about 10 watts for the VRMs. So 55 watts? Maybe as low as 45 watts depending on fuzzy numbers. llano looks to me to be a smash hit with plenty of thermal headroom.
 
hans007 said:
yeah i dont think idle is going to make a huge difference.

on my llano at stock everything, idle isl ike 30W but full prime 95 load is somethingl ike 131W from the wall on an 80plus bronze psu.

so at load it has actaully huge power consumption for a 32nm chip
Click to expand...

You arnt by chance ian cutress are you?

Horrible review where he tested llano power consumption with a 1000 watt power supply, it was 80 plus as well.

http://www.anandtech.com/show/4499/...5m1i-deluxe-ecs-hdci-and-zotac-fusion350ae/11
 
I think i posted a comment somewhere saying they should add a static 200 watt load to those big supplies, then subtract that 200 watts from all test readings. They just gotta calibrate the load so it reads 200 watts at the wall. That will push the supply into its most efficient range so meaningful tests can be done on low power systems. Of course the load would need to be distributed to 3.3V and 12V... It wouldnt be exactly easy but load resistors are a dime a dozen.
 
Not surprising, mobile parts can do 35-45W (albeit with lower clocks) and 65W desktop versions with the same/similar clocks are supposed to be coming out.

Undervolting is always a great way to cut back on heat, noise, and power consumption at stock speeds, there's really not much reason not to do it IMO if you don't plan on OCing. My X4 955, for example, is undervolted from 1.4V to about 1.23V.
 
hans007 said:
yeah i dont think idle is going to make a huge difference.

on my llano at stock everything, idle isl ike 30W but full prime 95 load is somethingl ike 131W from the wall on an 80plus bronze psu.

so at load it has actaully huge power consumption for a 32nm chip
Click to expand...

That's pretty crappy to be honest considering how weak the Llano CPU is. A stock 2500 SB doesn't even hit 110W with a 6970.

http://www.xbitlabs.com/articles/cpu/display/core-i5-2500-2400-2300_10.html#sect0
 
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Correct me if I'm wrong but isnt power consumption merely a simple measure of clock speed, transistor count, and voltage? If you do not lower the voltage, then why would you expect power consumption to be better? From what I've seen they did not reduce the voltage when they went to 32nm. God knows why, but at least we know they can run at lower voltage.
 
sm625 said:
Correct me if I'm wrong but isnt power consumption merely a simple measure of clock speed, transistor count, and voltage? If you do not lower the voltage, then why would you expect power consumption to be better? From what I've seen they did not reduce the voltage when they went to 32nm. God knows why, but at least we know they can run at lower voltage.
Click to expand...

Not transistor count, rather it's the chip's capacitance (the thing that changes per tech node).

Also it is easy to point to select examples of lowered voltages on a few Llano's in the field but surely you aren't about to presume AMD set the Vcc for the general SKU's without good reason 😕

The required operating voltage at any given clockspeed is always going to be dependent on the operating temps.

If everyone is willing to operate their CPU at nothing higher than a max of 45C then AMD could lower the Vcc accordingly, with the understanding that trying to operate your chip at 55C will then result in it crashing or some such.

AMD is full of smart people, surely you'd agree, and the stock voltage on Llano is as it is for good rational reasons that ought not be readily discarded based on a few examples of successful undervolting.
 
Idontcare said:
When I see first-hand reports like this it doesn't surprise me at all that bulldozer was delayed. They are probably wrestling with some serious power-consumption issues.
Click to expand...

Could this be related to some LP type of transistors? And how would you interpret these ES P-State definitions:
Code: 
P-State	FID 0x14 - VID 0x0B - IDD 12 (18.00x - 1.412 V)
P-State	FID 0xE - VID 0x0E - IDD 10 (15.00x - 1.375 V)
P-State	FID 0xA - VID 0x16 - IDD 10 (13.00x - 1.275 V)
P-State	FID 0x7 - VID 0x1B - IDD 9 (11.50x - 1.212 V)
P-State	FID 0x4 - VID 0x21 - IDD 8 (10.00x - 1.137 V)
P-State	FID 0x1 - VID 0x26 - IDD 6 (8.50x - 1.075 V)
P-State	FID 0x10C - VID 0x30 - IDD 6 (7.00x - 0.950 V)
Could IDD stand for specific levels of max. current? I noticed a relatively big jump in voltage going from 3rd to 2nd entry, while IDD stays the same.
 
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Maybe the IDD 10 thing appearing twice is a typo. And as a result of that typo, 100mV is added to the chip for no good reason other than pure stupidity. I would seriously not be surprised if this sort of thing happens at AMD. 😛
 
Dresdenboy said:
Could this be related to some LP type of transistors? And how would you interpret these ES P-State definitions:
Code: 
P-State    FID 0x14 - VID 0x0B - IDD 12 (18.00x - 1.412 V)
P-State    FID 0xE - VID 0x0E - IDD 10 (15.00x - 1.375 V)
P-State    FID 0xA - VID 0x16 - IDD 10 (13.00x - 1.275 V)
P-State    FID 0x7 - VID 0x1B - IDD 9 (11.50x - 1.212 V)
P-State    FID 0x4 - VID 0x21 - IDD 8 (10.00x - 1.137 V)
P-State    FID 0x1 - VID 0x26 - IDD 6 (8.50x - 1.075 V)
P-State    FID 0x10C - VID 0x30 - IDD 6 (7.00x - 0.950 V)
Could IDD stand for specific levels of max. current? I noticed a relatively big jump in voltage going from 3rd to 2nd entry, while IDD stays the same.
Click to expand...

Yeah those IDD's can't be actual current draws (in amps), the numbers are too low by a factor ten to even be in the ballpark.

Further, as you noted, any change in operating frequency is going to result in a change in current draw. But the 2nd to 3rd entry changes involve a change in the multiplier from 13x to 15x which would drive a change in the current draw.

So if IDD represented current then there should be a notable change in the IDD value for those two P-States.

I really don't know what would be pushing the power-consumption to higher levels other than the generic observation that gate-first HKMG integration is a trade-off of having higher gate density with lower drive-currents versus that of a gate-last integration scheme.

To make up for the lowered drive currents you must dial up the Vcc accordingly such that you achieve the necessary drive currents to satisfy your clockspeed aspirations.

Intel's gate-last integration scheme gives it an intrinsically higher drive-current for a given operating voltage meaning they can set the operating voltage lower while attaining a given clockspeed (for a given circuit, all things considered equal), but that comes at the expense of an intrinsically lower gate-density (fewer chips per wafer).

What we don't know is how much of this fundamental device physics limitations are in play versus how much of what we are seeing is simply nothing more than your basic garden variety "new node maturity" teething problems.

This is where AMD's (now GloFo's) well known and well respected APC (advanced process control) will be brought to bear and make a critical difference in the node's rate of maturation. Thinking of the difference between those initial PhII X4's and the successor PhII X6's that had higher clocks and more cores but not higher power-consumption.
 
Idontcare said:
Yeah those IDD's can't be actual current draws (in amps), the numbers are too low by a factor ten to even be in the ballpark.

Further, as you noted, any change in operating frequency is going to result in a change in current draw. But the 2nd to 3rd entry changes involve a change in the multiplier from 13x to 15x which would drive a change in the current draw.

So if IDD represented current then there should be a notable change in the IDD value for those two P-States.
Click to expand...
I checked my manuals. There is indeed a defined Idd value per core, 8 bit, divisor 1/10/100A. But I couldn't see a relation to the IDD values. One explaination could be digital APM and the power management's estimations of drawn currents. In this case those IDD numbers could provide a cap, similar to the TDP cap technology. Actually this could be representing this tech, since an estimated TDP at a set voltage (for the active P-State) would work by estimating current draw.
 
Looking at a A4-3300 for a bitcoin mining rig with 3x 5870s... I've seen reviews on Newegg that have these drawing 4 watts at idle.
 
Why does IDC's post say 8-2-12, and EnderK's post says "Today", when today IS 8-2-12

Edit: Nevermind, their posts are 8-2-11.
 
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