Definately new mobo's will be required. I guarantee it.
Is that sarcasm, A4A? (I'm asking seriously)
Threshold voltage (Vt) is a property of the transistors on the chip. The mechanism of Vt variation to transistor operation is not easily explanable in detail without pictures, but it can be summed up succintly by saying that "a low Vt device is faster than a high Vt device, but a low Vt device uses a lot more power than a high Vt device." So this transistor property allows a choice between, among other things, speed and power. Typically the process gurus at fab companies choose one Vt for all of the devices and stick with the best compromise between speed and power that they can. There have been thoughts for quite a while among researchers about implementing low-Vt and high-Vt devices into the same process to try to gain the speed advantage of low-Vt devices in a circuit while using the high-Vt devices to control the overall power of the circuit. Or another idea is to just use low-Vt in a few important circuits that need to perform quickly and use high-Vt everywhere else on the chip. Ideas like these have been mentioned theoretically in research papers throughout the early and late 90's, and dual-Vt has recently been implemented in many of the major fab processes in the world.
TSMC has multiple-Vt capabilities, IBM, UMC, and Intel all have the capability - although I'm sure how many are implementing it in shipping products. IBM revealed at the ISSCC conference last year that they had opted for the "make all of the important circuits low-Vt" approach and implemented a "low-Vt" budget to minimize power in their Power4 microprocessor. Intel revealed at the 2000 IEDM conference in San Francisco that it was being implemented on Intel's 0.13um process - although I'm not sure if any products were revealed to contain this technology since that time.
But back on the subject. Dual-Vt technology adds slightly to the cost of manufacturing the chip (it adds additional steps and mask layers to the flow), but it doesn't affect the end-user at all. It certainly wouldn't require a motherboard upgrade.
On the subject of the research that Anand is mentioning, I believe that he is referring to research MRL has been working on for low-power, high performance SRAM. The paper presented by Ye et.al. at the 2002 VLSI Symposium (Circuits) conference this year talks about MRL's research in this area: "A 6GHz, 16KB L1 Cache in a 100nm Dual-Vt Technology Using a Bitline Leakage Reduction Technique". In this case, the technique described uses two voltages and dual-Vt transistors in a cache to try to maximize performance while minimizing power. This sounds similar to what Anand described in the update.
BTW, Anand, I wish I was there too.
🙂
