Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[JasonLD]

Cant see Intel doing any fabs without subsidies. They would have to have the confidence that 7 nm and any other future node won't take 5 years to get to decent yield.

What is the % you consider to be a decent yield?

 

[jpiniero]

What is the % you consider to be a decent yield?

Competitive with TSMC.

 

[JasonLD]

Competitive with TSMC.

Competitive with TSMC's reported 70% yield is great, but just needs to be somewhere between Samsung's 35% and 70% to be commercially viable.
Then again, Intel is going in with a learning node before HV nodes, (4nm before 3nm, 20A before 18A), Initial yield may be much better than 10nm.

 

[DrMrLordX]

The Angstronomics site doesn't exactly have a long track record (it started about a month ago from what I can tell) but the name chosen for it may indicate a certain bias towards Intel. The article on TSMC N5 sure seems like a "TSMC sucks, go Intel" agenda is being pushed, we'll have to see how they handle Intel when articles with them as the subject are written.

An article about N5 is little more than poring over recent history. They may as well write about Intel 10nm or 10nm+. Don't see em doing it yet, though.

Cant see Intel doing any fabs without subsidies. They would have to have the confidence that 7 nm and any other future node won't take 5 years to get to decent yield.

Right. May as well leave someone else holding the bag.

 

[John Carmack]

Why would TSMC cite theoretical density, if they are actually producing significantly less dense chips?', and the answer is simple, they want investors and clients to believe they are further ahead of the competition (Intel, Samsung) ... grreat article exposing tge marketing of these foundries 😏

He's just exposing marketing lies.. we need full transparency from companies

That place reads like what I'd expect from a purported engineering and economic analyst who aims to teach us behind a sketchy pseudonym and Intel branded banner.

I'm glad you continue to expose marketing lies here with us.

 

[Ajay]

Cant see Intel doing any fabs without subsidies. They would have to have the confidence that 7 nm and any other future node won't take 5 years to get to decent yield.

They need the subsidies so that their shareholders don’t have a heart attack when profits crash and then dump all their stock. Weirdly, Gelsinger has a fiduciary responsibility to seek out subsidies in order to protect the company's cash flow, etc.

 

[Ajay]

I believe this has been posted b/4. But, if you haven't done so - read through the whole thread. There is much more there than just Jim Keller's comments.

https://twitter.com/x/status/1539994595769176064

 

[pakotlar]

I believe this has been posted b/4. But, if you haven't done so - read through the whole thread. There is much more there than just Jim Keller's comments.

https://twitter.com/x/status/1539994595769176064

That all sounds pretty bad.

 

[Ajay]

That all sounds pretty bad.

Well, it does show where Intel has really screwed up on the design side. No wonder Keller was yelling so often (according to Raja). The multi-chip technologies are so dis-integrated it's a wonder that Intel has anything running (and part of why SPR is so late).

 

[pakotlar]

Well, it does show where Intel has really screwed up on the design side. No wonder Keller was yelling so often (according to Raja). The multi-chip technologies are so dis-integrated it's a wonder that Intel has anything running (and part of why SPR is so late).

Intel has so much potential. I hope they sort themselves out.

 

[witeken]

I believe this has been posted b/4. But, if you haven't done so - read through the whole thread. There is much more there than just Jim Keller's comments.

https://twitter.com/x/status/1539994595769176064

Sounds BS. It comes across as "Intel is incompetent Intel suxx". Lakefield was the world's first (and still only) 3D packaged logic stacking product in the world. Ponte Vecchio is only extending Intel's advanced packaging leadership, and Meteor Lake will widen the gap even more. Ponte Vecchio was only delayed because they needed to port from 7nm to N5. Meteor Lake is delayed because of 7nm delay. To say that Intel can't do chiplets is ridiculous and untrue.

 

[DrMrLordX]

Ponte Vecchio is only extending Intel's advanced packaging leadership

Seems like it's advancing that leadership rather slowly.

Ponte Vecchio was only delayed because they needed to port from 7nm to N5.

Yeah. Because Intel 7nm/Intel 4 was totally not ready. Even the best packaging tech in the world will do you no good if the required fab tech isn't functioning yet. Oh and Lakefield was really not a good product either, so that's not bragable.

 

[maddie]

Sounds BS. It comes across as "Intel is incompetent Intel suxx". Lakefield was the world's first (and still only) 3D packaged logic stacking product in the world. Ponte Vecchio is only extending Intel's advanced packaging leadership, and Meteor Lake will widen the gap even more. Ponte Vecchio was only delayed because they needed to port from 7nm to N5. Meteor Lake is delayed because of 7nm delay. To say that Intel can't do chiplets is ridiculous and untrue.

View attachment 63686

Ode to the power of modern marketing on some.

 

[Ajay]

Sounds BS. It comes across as "Intel is incompetent Intel suxx". Lakefield was the world's first (and still only) 3D packaged logic stacking product in the world. Ponte Vecchio is only extending Intel's advanced packaging leadership, and Meteor Lake will widen the gap even more. Ponte Vecchio was only delayed because they needed to port from 7nm to N5. Meteor Lake is delayed because of 7nm delay. To say that Intel can't do chiplets is ridiculous and untrue.

View attachment 63686

PV is not even meant to be a high volume product. It is, essentially, a bespoke product for large HPC customers. My understanding is that it was very hard to ramp with poor initial yields. This could be viewed as reasonable, given the the number of chiplets and advanced packaging technology. Now, I don't know if it will be making it's way into workstations, or what Intel's projections are for PV's market share. The problem is that Intel's high volume advanced packaged products are also being delayed - like SPR. What is the problem with SPR, and why has it been delayed for a year?

The thread in twitter, and bits and pieces that have come out from other sources, indicated that Intel has a significant problem with design integration (lacking in some ability to take a holistic view of the entire process from start to finish). It appears to be structural, that is, it is rooted in a system that management has failed to focus on these necessary technologies. Groups develop impressive interconnect technology (EMIB, Foveros) and then soft of drop the ball in transitioning that into the design process inorder to develop real products in a timely manner. That appears to be changing - but it's slow and fraught with risk because of the design team of 10K individuals. I hope that they pull it off - I have no hate for Intel and I want them to succeed, they have a great history as a premiere American technology company.

 

[Exist50]

Meteor Lake is delayed because of 7nm delay.

If you take Intel's public statements at face value, Meteor Lake won't be coming till 2-3Q after Intel 4 is ready.

 

[Saylick]

TSMC: N2 To Start With Just GAAFETs, Add Backside Power Delivery Later

www.anandtech.com

Intel might actually take the process lead if they get GAAFET + BPD working before TSMC, but that's a big 'if'. TSMC, as usual, is taking the slow and measured approach by introducing one big variable at a time, which to be fair is what Intel is doing with their internal ribbonFET-only node in 2023, but we will let history be the judge. Furthermore, when TSMC introduces BPD, it will be in the form of buried power rails, while Intel is going with power vias. Given their slow and steady approach to things, TSMC will probably move up the complexity ladder and implement power vias at some point after they get their first iteration of BPD working.

 

[DisEnchantment]

Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture

Optimized 3nm process achieves 45% reduced power usage, 23% improved performance and 16% smaller surface area compared to 5nm process

news.samsung.com

Samsung's GAA is here.

Healthy performance and efficiency it seems from official PR for 3GAE.

Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.

Taking the density of 5LPE at 125 MTr/mm2 going by consensus, that would be a 145-150MTr/mm2. Just about on par with N4.
Good thing is that they got it out the door, now they can iterate on it.
But that big efficiency gain is going to help their chips immensely.

3GAP next year will improve on that with more density and slightly more efficiency and performance, should be able to take their density close to 190 MTr/mm2.
At least they can have their title, first to GAA.

 

[trivik12]

Question is what would be the 1st product made on the node. I Hope we see a mobile SOC using that node. Do we know if there will be a exynos flagship for 2023 or are they skipping next year?

 

[Henry swagger]

Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture

Optimized 3nm process achieves 45% reduced power usage, 23% improved performance and 16% smaller surface area compared to 5nm process

news.samsung.com

Samsung's GAA is here.

Healthy performance and efficiency it seems from official PR for 3GAE.

Taking the density of 5LPE at 125 MTr/mm2 going by consensus, that would be a 145-150MTr/mm2. Just about on par with N4.
Good thing is that they got it out the door, now they can iterate on it.
But that big efficiency gain is going to help their chips immensely.

3GAP next year will improve on that with more density and slightly more efficiency and performance, should be able to take their density close to 170 MTr/mm2.
At least they can have their title, first to GAA.

I want more information from Samsung on the hp libraries of the node... intel 4 is the node with the most hp density

 

[Doug S]

Good thing is that they got it out the door, now they can iterate on it.
But that big efficiency gain is going to help their chips immensely.

Only if they can actually get decent yields, which has been a problem for them with new nodes for a few years now.

Maybe they don't care if they have terrible yields for Exynos SoCs, since they might as well use the capacity internally if they can't sell it. They'd probably like to be able to beat Qualcomm SoCs made on TSMC for once, even if it is a pyrrhic victory.

 

[DisEnchantment]

I want more information from Samsung on the hp libraries of the node... intel 4 is the node with the most hp density

Helloo ... this is GAA not FinFET. There is no HP or HD library.
It is available today. You might have to wait another year for Intel 4.

 

[DrMrLordX]

Samsung's GAA is here.

Healthy performance and efficiency it seems from official PR for 3GAE.

Huh! Looks like 3GAE won't be an internal node after all. Good for Samsung.

 

[Doug S]

Huh! Looks like 3GAE won't be an internal node after all. Good for Samsung.

How is it not an internal node if they won't open the door to external customers until 3GAP? When TSMC announces mass production of a given node they talk about "many customer tapeouts" and when customer shipments will begin. They often mention wpm volume.

Samsung just says it has begun manufacturing, with no mention of customers not even internal ones. This sounds more like risk production, since their internal needs for an advanced node are quite modest. What do they use it for, other than Exynos - a new version of which won't ship until the Galaxy S23 next spring? They could run at a single digit yield and pile up enough for that launch easy.

I'm willing to bet we don't see any 3GAE based products announced this year.

 

[Lodix]

How is it not an internal node if they won't open the door to external customers until 3GAP? When TSMC announces mass production of a given node they talk about "many customer tapeouts" and when customer shipments will begin. They often mention wpm volume.

Samsung just says it has begun manufacturing, with no mention of customers not even internal ones. This sounds more like risk production, since their internal needs for an advanced node are quite modest. What do they use it for, other than Exynos - a new version of which won't ship until the Galaxy S23 next spring? They could run at a single digit yield and pile up enough for that launch easy.

I'm willing to bet we don't see any 3GAE based products announced this year.

Samsung doesn't have "internal" nodes. It is BS that people keep repeating and now they think it is a reality.

They don't open to external customers? Again another lie. It is a myth that people keep repeating and now becomes the truth.

Samsung Foundry always offers their "Early" version on their processes to their costumers. Clear examples Qualcomm constantly producing chips on that nodes.

It is just a marketing name. And the iteration the next year with more mature yields is normally the "Plus". But doesn't have anything to do with "internal" or "external" nodes.

Samsung never announces their mass production as you mention. So it means nothing.

And precisely they are announcing here that they are making "chips for high performance, low power computing application" ( expeculated to be an ASIC for mining for a Chinese costumer ) and plans to expand to mobile processors." So they are also going to produce mobile SoCs this year.

 

[Exist50]

Samsung doesn't have "internal" nodes. It is BS that people keep repeating and now they think it is a reality.

They don't open to external customers? Again another lie. It is a myth that people keep repeating and now becomes the truth.

Samsung Foundry always offers their "Early" version on their processes to their costumers. Clear examples Qualcomm constantly producing chips on that nodes.

It is just a marketing name. And the iteration the next year with more mature yields is normally the "Plus". But doesn't have anything to do with "internal" or "external" nodes.

Samsung never announces their mass production as you mention. So it means nothing.

And precisely they are announcing here that they are making "chips for high performance, low power computing application" ( expeculated to be an ASIC for mining for a Chinese costumer ) and plans to expand to mobile processors." So they are also going to produce mobile SoCs this year.

Samsung showed a roadmap that completely skipped 3GAE.

It's highly doubtful that the process is close to ready for real mass production. Maybe sometime in '23, but right now it seems they're just starting risk production.