Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Dayman1225]

looks like 5 nodes in 4 years already slipping

What? 7, 4, 3, 20a and 18a are those 5 nodes and they’re all on track according to Intel

 

[Exist50]

part of a slide in the Intel Foundry Model Investor WebinarView attachment 82063

This is probably the most honest heads to heads comparison I think I've ever seen from Intel's fabs. It's really only with 18A that they have something worth using. We'll see if they're able to recover.

 

[DrMrLordX]

You’re right. They messed up 10nm so they’re doomed to fail forever now. Intel and Samsung might as well close up shop. Clearly only TSMC is capable of doing this now and forever; there must be something special in the water in Taiwan.

Nah, not Samsung. Just Intel. Intel is already positioning themselves to spin off their fabs.

 

[DavidC1]

Then how is that relevant to the fact that Intel cancelled every product of theirs on Intel 4 except for a heavily-delayed Meteor Lake that isn't a very good product?

Some of the lackluster results are due to the process, I wouldn't doubt. But mostly it's the design.

I won't be surprised if it's the same with 20A and 18A, where 20A underperforms, and why they might be using N3 for certain Arrowlake variants. That would mean Intel 3 and 18A would be greater advancements on a product level than papers suggest otherwise.

Further evidence is Intel themselves admitting that they will be behind up until 20A - after that they'll be ahead. Checking boxes for features such as RibbonFET and PowerVia is nice, but whether it's the best implementation of it is a different story. For example, Intel didn't need copper interconnect on 0.18u to significantly outperform the 0.18u copper process AMD was using. The drive current differences were in upwards of 30% in favor of Intel!

They say the devil is in the details, and RibbonFET and PowerVia are not those. If those were the only criteria, why would they say it takes until 2025 to have unquestioned leadership?

By the way the guy claiming 400MT density for 20A seems to be from SeekingAlpha, so take it with a grain of salt. Although in the article he mentions Bob Swan talking about 5nm(logically would be the previous name for 20A) being 2x the density, so we'll see.

 

[H433x0n]

Some of the lackluster results are due to the process, I wouldn't doubt. But mostly it's the design.

I won't be surprised if it's the same with 20A and 18A, where 20A underperforms, and why they might be using N3 for certain Arrowlake variants. That would mean Intel 3 and 18A would be greater advancements on a product level than papers suggest otherwise.

Further evidence is Intel themselves admitting that they will be behind up until 20A - after that they'll be ahead. Checking boxes for features such as RibbonFET and PowerVia is nice, but whether it's the best implementation of it is a different story. For example, Intel didn't need copper interconnect on 0.18u to significantly outperform the 0.18u copper process AMD was using. The drive current differences were in upwards of 30% in favor of Intel!

They say the devil is in the details, and RibbonFET and PowerVia are not those. If those were the only criteria, why wouldn't they say it takes until 2025 to have unquestioned leadership?

By the way the guy claiming 400MT density for 20A seems to be from SeekingAlpha, so take it with a grain of salt. Although in the article he mentions Bob Swan talking about 5nm(logically would be the previous name for 20A) being 2x the density, so we'll see.

The latest Specint results taken by David Huang seem to backup the claims made by Intel in their technical documents for Intel 4 (roughly ~20% perf/watt).

I don’t know where that puts them relative to TSMC. I don’t know if there’s a good way of accurately judging the relative performance against N4P.

Intel’s use of 6VT cells for most of the compute tile sans 2x PCores is encouraging too. Went from UHP cell spam to HP cell spam.

 

[Aapje]

If we assume not only TSMC, but Samsung also gets gutted in an escalation...

Why would Samsung get gutted? The core of their company is in Korea.

I can see them dancing on TSMC's grave actually, especially if they manage to smuggle some of the key TSMC workers out of Taiwan and put them to work for Samsung.

 

[moinmoin]

TSMC backing off again. No end to their excuses. They just don't really want a US fab IMHO (even though they have a point about the lack of execution on the CHIPS funding).

TSMC delays 3nm Arizona fab by a year, cites lack of U.S. subsidies and waning demand

TSMC faces another setback in the U.S.

www.tomshardware.com

To be fair this is about phase 2 which is some form of N3, a node not really settled yet. Nobody wants a node that nobody wants. N4 as part of phase 1 is scheduled to go live in 2025.

 

[Thunder 57]

TSMC's US efforts have been a disaster so far.

Diversifying out of Taiwan, esp because of the invasion threat, is a good idea. But perhaps they need to find a different country. One more to their liking.

A big problem is the difference in culture. Americans don't want to slave away like they do back at TSMC.

 

[Doug S]

Intel messed up with 10nm. But TSMC messed up with both N3 & N2. With N3, the first node N3B was a colossal mess up & they're moving it in bulk to N3E which isn't up and running yet (delayed). With N2 they just couldn't get backside power delivery working on time. And by the time they actually launch N2 with BSPD, Intel will be rolling out 14A High-NA EUV.

Like Pat clearly mentioned, 18A is gonna be better than N2. And naturally, 14A High-NA is gonna be light years ahead of all TSMC offerings in 2026.

Intel process leadership is now just a matter of time. And it starts this year.

You are making a very false assumption that "with N2 they couldn't get backside power delivery on time".

TSMC said that N2 with BSPDN will follow six months after the release of N2, and that TSMC is making that optional because it increases cost and some customers may need/want it. Also note the timing, with N2 hitting mass production in H2 2025, that means N2+BSPDN hits mass production in H1 2026. Guess which huge customer cares about being able to begin mass production before H2, and upon whose schedule TSMC has rolled out every process (except N3 where yes they screwed up but not nearly as badly as Intel did with 10nm which was delayed by several YEARS)

Now maybe you say you don't believe TSMC's statements about BSPDN, but if so why do you accept Intel's statements such as 18A being better than N2? You must either work for Intel or own millions in their shares because you aren't looking at this remotely objectively. You buy everything they say without any question, dismiss the 10nm debacle as "a mess up", and look at everything TSMC does in the most negative light possible.

 

[SiliconFly]

...the subtitle equates 10A to 1 nm. 10A is meant to look like 10 Å (Angstroms), but nothing about 10A is actually 1 nm.

Same applies true for TSMC as well. Nothing about N2 is actually 2nm. And nothing about N3 or N5 is actually 3nm or 5nm respectively. Likewise, there is nothing 7nm in TSMC N7. It's all marketing names.

Truth is, it's been more than 2 decades since node names actually corresponded to actual physical transistor metrics like gate length, pitch, etc. Doesn't hold true for TSMC, Samsung, Intel or GF anymore.

What matters is how far ahead Intel 1nm node is compared to existing nodes like TSMC 2nm. I'd say pretty much.

 

[moinmoin]

All those tables comparing the technical specs of each foundry processes with each other all miss one important detail, the resulting yield rate.

And the max achievable frequency (which directly correlates with performance like Intel shows itself with both 14nm and 10nm).

 

[DisEnchantment]

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025
With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFETTM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

3nm’s logic yield is approaching a similar level to the 4nm

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022

Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices

Details were disclosed at the company’s 5th Annual Samsung Foundry Forum

news.samsung.com

Its official, 3GAE is still alive. Seems they have been very secretive about GAA

• Density would be comparable to N5 (my guess)
• But the performance and efficiency is much improved compared to 5LPE.
• Yield similar to 4LPE, not bad on first gen GAA
• Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022

I guess 4LPP and 3GAE will be the lead processes in 2022.
50% power efficiency gain from 5LPE(P?) --> 3GAE is quite impressive.
30% perf gain from 5LPE(P?) --> 3GAE is equally impressive.
Density is OK, important but even TSMC's figure were very ideal case only and not achievable.
These are much closer to the 2019 figures.
I guess the previous Marketing PR was probably a red herring.
Waiting for David Schor to dig deeper.
Really looking forward to see chips on this.

 

[Hitman928]

So more of a competitor to, say, GF FDX nodes.

No, those are more advanced even. Tower has 45nm+ nodes with lots of non-bulk CMOS options. They've got some good stuff, just not things this forum would probably be too interested in, generally. I've actually used Tower Semi a few times and have an upcoming project slated to use them again. I'm really hoping Intel doesn't screw this up and make things difficult for their customers when trying to integrate Tower into Intel's 2.0 model.

 

[Thunder 57]

That forum is full of disgruntled ex-employees with an axe to grind. Of course they blame everything on immigrants.

H1B's are bad.

 

[qmech]

So reduction of just 30mm2 in die area can result in a temperature hike of 30 degrees Celsius??? :-O

7 nm lithography process - WikiChip

If you (and other people on this forum) are right, why is WikiChip comparing Intel 4 to N7?

The WikiChip overview pages were made back when Intel called their Intel 4 process for "7nm". That's why it's in a section with N7 under the label "7nm lithography".

It has absolutely nothing to do with any other characteristic of the process.

If you want some insight from WikiChip into Intel 4, you could read the recent article on it:

A Look At Intel 4 Process Technology

A look at Intel's next-generation high-performance process technology, Intel 4.

fuse.wikichip.org

From the conclusion:

On paper, those PPA characteristics positions the company’s new Intel 4 process at performance levels better than TSMC N3 and Samsung 3GAE. On the density front, Intel 4 appears highly competitive against N3 high-performance libraries.

....

With the Intel 4 process detailed in this article, the company’s ability to regain its leadership position in the semiconductor industry rests entirely on its execution.

 

[Saylick]

Caught this article about SRAM scaling, or the lack thereof, today: https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/

Begun, the SRAM stacking war has.

 

[moinmoin]

Those words boosted Intel's after hours trading.

Ain't that nice?

Personally I think stock trading is bad at accurately reflecting the actual worth of businesses. Intel still did put a lot of importance into it, with stock buybacks and dividends, at times when it should have spent into its business instead.

Only thing is, that didn't even help them. Current market valuation of select companies (feel free to add more):

• Apple: 2833 B
• Nvidia: 982.3 B
• TSMC: 512.6 B
• Samsung Electronics: 376.9 B
• AMD: 192.4 B
• Intel: 129.8 B
• Qualcomm: 129.0 B
• MediaTek: 39.0 B
• GlobalFoundries: 32,75 B

 

[A///]

Discord is a 'social media app' essentially. I use it to keep in touch with friends, and use voice chat with my friends when playing video games. A lot of companies/websites have their own discord servers, which are essentially giant group message forums. Chips and Cheese, the website, created their own server, which you can join. Intel has their own server, called Intel Insiders IIRC, where you can talk about their products. The general PC building subreddit has their own discord server as well. Often there are the website founders/officials in those servers as well. The authors of many Chips and Cheese articles are in the Chips and Cheese server, several Intel engineers are in the Intel Insiders server, etc etc.
A lot of useful information are dropped in those servers. For example, rumors are talked about in the Chips and Cheese server, as well as other technical information such as discussions about CPU architecture, nodes, GPUs, and other information that flies over my head. A very good place to learn and discuss opinions. An example of info from the Intel Insiders server was that one Intel engineer who confirmed that MLID's ARC 'A780' leak was infact, complete BS, like Ryan Shrout mentioned on twitter as well. Another great place to talk about technology.

we call that an msn messenger room.

 

[moinmoin]

IMO, it’s already over and TSMC lost process leadership for HPC.

So you say Intel is process leader in backside power delivery? What concrete parameters of silicon quality affects that? And why would that only matter in HPC?

Edit: Having read the article, the author himself refers to EUV as a comparison point recalling that TSMC had EUV back in 2016 while Intel finally got it working in Intel 4 this year. And Intel wants BSPDN working next year while TSMC plans to have it in 2026. Let's see how this timeline turns out.

 

[Dayman1225]

No specific numbers but an Intel VP, William Grimm, Vice President, Director of Product Engineering for Logic Technology & Development has stated Intel 4 is yielding “higher than expected”

https://x.com/tech_reve/status/1694146841867428118?

https://x.com/tech_reve/status/1694146843381477433?

 

[maddie]

I doubt it will be soon. The range of supply chain partners includes some of the most capable companies in the world for their area of specialty. ASML depends on many hundreds of partners to supply components for their EUV machines.

I fail to see this. If one solution entails X, why would you think another path can't work? Do we really understand the scale of China? You do say this.

some of the most capable companies in the world for their area of specialty

I assume this to mean that close to comparable expertise also exists elsewhere. Complacency can bite. I'm very skeptical of these arguments, as I've seen them repeated and failed many times previously.

edit: Merely knowing a solution exists can speed development and ASML themselves worry about this sanction policy being detrimental.

 

[Ajay]

I think TSMC offered Apple a deal just so something will use N3B to amortize whatever tools are specific to N3B.

Well, that and Apple was committed - they needed to get A17 out (for at least the Pro models)and N3E would be too late.

 

[controlflow]

I'm aware of the stupid naming conventions. While TSMC 7 and Intel "7" (10nm++ SF) are similar in density and pitch, one still out performs the other. Intel's node gives them the ability to clock higher at the cost of heat and power. Are we really ignoring that Intel needs that plus 24 total cores with 8 of them having HT to compete or uncomfortably beat a 7950X while using more power?

Intel can notch down a few nodes in the next few years but their design choices leave a lot to be desired. Needing to pump out higher frequency and more cores to match 16 SMT cores is sad.

I think Raptor Lake does a reasonable job at competing with Zen 4 when you consider that the 7950x is on TSMC N5. Yes Raptor Lake is less power efficient then Zen 4 and it is pushed to pretty high power consumption to match or beat Zen 4 which has a node advantage.

Raptor Lake seems to match or beat TSMC N7 products like Zen 2 and 3 though. I think it is fair to criticize Intel for their design choices with Golden Cove being too large or even the big core small core strategy with the incompatible ISAs, but I'm not understanding the criticism of Intel 7 as being some kind of misleading name when we are willing to accept TSMC N7. I think Intel 7 is generally as advertised.

 

[Panino Manino]

Is Murrica starting to become concerned about the progress of the Chinese fabs?

U.S. to Extend Permission for Samsung and SK Hynix to Export New Tools to China

But there is a catch

www.tomshardware.com

Seems like Chinese companies like Huawei will be able to buy memory chips from the Koreans again.

 

[H433x0n]

Yeah wouldn't it be great if all the fabs came together and joined into one? But seriously tho there isn't a true monopoly in semi-fab and TSMC only has cutting edge nodes for so long. Before their 7nm became mainstream, which was barely 4 years ago, they were considered on the same level as Samsung and thought to be behind Intel.

Calling TSMC as an extension of AMD and not Apple would say to me that you don't actually mean what you are saying, or that you are completely ignorant of reality.

I actually agree with everything you wrote.