Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

NostaSeronx

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GlobalFoundries Malta 2023 going into Q4:
~20k average active wpm for 12LP family nodes
~15k average active wpm for 45SOI family nodes

There is an additional inactive quantity still available being ~30k wpm. Which has likely been reserved for 22FDX++/12FDX for sometime this year. Next-gen high mobility substrate was pushed through SOITEC/GF agreement 2023. Which should allow for the below to occur:

22FDX++ = Tensile NMOS, improved Compressive PMOS // 2016 = 22FDX => 2020 = 22FDX+ => 2024 = 22FDX++
12FDX = smaller FEOL/BEOL, etc <-- Faster than 10nm FDSOI(STM)

Which leads to 2026+ for 6FX/3FDX
6FDX = Gen2 Compressive/Tensile, smaller FEOL/BEOL
3FDX = Gen3, smaller FEOL/BEOL

Additional new info:
6FDX; 56CPP/51CPP
3FDX: 48CPP/45CPP
Expect the BEOL to be smaller than FinFET alternatives. The numbers are expected cost versus 6nm FinFET and 3nm FinFET, not the actual nodes being deployed. The missing node is expected to be fulfilled by 12FDX. 12FDX Large CPP = 84~78 and 12FDX Small CPP = 70~64.

It is likely do to Fab8.1/8.2 power requirements that GF will forcibly move to Canon's NIL. For these nodes, going forward. AS it is the only tool that has power reduction from 193i. That can do leading edge BEOL dimensions, as FEOL for FDSOI doesn't need to go beyond SADP.

8.2(2025 start construction date) = Bleeding edge FDSOI
 
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uzzi38

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Oct 16, 2019
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But when has AMD ever aggressively used TSMC's latest process immediately after it is available?

Some might excuse that by saying "well Apple always takes all the initial supply" but if you're looking for a deep pocketed company that will be next in line behind Apple to take that supply that's Nvidia not AMD.

Heck if Nvidia doesn't get some real competition soon (and the AI bubble doesn't burst) they might overtake Apple as TSMC's biggest customer by revenue two or three years from now.
The AI bubble thing is definitely a matter of time, we're already seeing AI startups die out due to lack of being able to actually monetise to recoup the hardware costs.

As for AMD, you're going to see them be a lot more aggressive with nodes in the future. In particular for the Dense CCDs, those ones can use more cutting edge nodes, as they can benefit a good bit more from the improved density. Plus, with those CCDs being reserved for the server market, they naturally get higher margins per CCD, which also means they can afford the extra cost of more cutting edge nodes. I wouldn't be surprised if Zen 6 Dense lands on N2, I'll put it that way.
 
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Hitman928

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N2 is really a H2 2026 product just like N3E is H2 2024 product, while volume manufacturing happens a year earlier.

When TSMC goes HVM, products can typically start appearing ~6 months later (N5 was HVM in Q2 2020 and Apple had products on shelves with it by Fall 2020). It depends on when the products are ready though. N3B HVM was about 6 months late and so it missed the needed window for Apple to use it in 2022 and there weren't really any customers for it until Apple's fall refresh. Intel's products using it were still a bit ways away and everyone else waited for N3E.
 

SiliconFly

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A nice video by HY about BSDP.


I did connect with him once when he was making the video. Some of the hilights of the video are:

(1) BSPD actually ends up not only improving voltage droop thereby improving efficiency but also Fmax at the same time.
(2) Transistors aren't flipped anymore with BSPD during the manufacturing process (actually flipped twice?).
(3) The signal wires on top connect to the substrate thru TSVs that go thru both the silicon and the PDN.
(4) He didn't talk about the heat dissipation issue, but I think CPUs will have trouble hitting Fmax due to this.
 

maddie

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When everyone else is moving to N3E, Intel appears to be the only one with N3B.
Intel panicked and reserved wafers due to fears of losing access to the latest and greatest. Now it's surpassed and they're stuck. In spite of all the bombastic talk, by their actions you will know them. You, especially, should take note of this.
 

maddie

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A nice video by HY about BSDP.


I did connect with him once when he was making the video. Some of the hilights of the video are:

(1) BSPD actually ends up not only improving voltage droop thereby improving efficiency but also Fmax at the same time.
(2) Transistors aren't flipped anymore with BSPD during the manufacturing process (actually flipped twice?).
(3) The signal wires on top connect to the substrate thru TSVs that go thru both the silicon and the PDN.
(4) He didn't talk about the heat dissipation issue, but I think CPUs will have trouble hitting Fmax due to this.
(4) He didn't talk about the heat dissipation issue, but I think CPUs will have trouble hitting Fmax due to this.

Fmax is whatever it is due to material and design choices. It might be lower vs without BSPD, but that IS the Fmax for those designs.
 

SiliconFly

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PTL tGPU will be on N3E and likely Celestial dGPU as well. What's the first N3E chip from AMD and Nvidia?
Panther Lake is 18A after ClearWater Forest. I remember seeing it recently (link, link).

Edit: Ok. PTL's tGPU on N3E sounds excellent. But battlemage is N3B I think & if PTL's tGPU is N3E, it has to be Celestial. But will Celestial be ready by then?
 
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SiliconFly

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Intel panicked and reserved wafers due to fears of losing access to the latest and greatest. Now it's surpassed and they're stuck. In spite of all the bombastic talk, by their actions you will know them. You, especially, should take note of this.
Well, N3E is better for sure. But we already have M3 built on N3B and it's good. So, the minor performance/efficiency hit shouldn't be a deal breaker.
 

SiliconFly

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Cost.

Check the number of masking steps needed.
Yep. It surely is a bit more expensive and complex and lower yield relatively. But it's already been paid up. There's nothing much to do except to go ahead. I think Intel's gonna be the only big customer who'll be using N3B going forward.
 

DavidC1

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Dec 29, 2023
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Panther Lake is 18A after ClearWater Forest. I remember seeing it recently (link, link).

Edit: Ok. PTL's tGPU on N3E sounds excellent. But battlemage is N3B I think & if PTL's tGPU is N3E, it has to be Celestial. But will Celestial be ready by then?
Battlemage dGPU is said to be on N4. It's only the iGPU in Lunarlake that is N3.
Fmax is whatever it is due to material and design choices. It might be lower vs without BSPD, but that IS the Fmax for those designs.
Not on x86 chips that clock above 5GHz. In those factory-overclocked chips(face it, that's why we have near zero OC headroom nowadays), heat density is entirely the factor in reaching such clocks. I don't think it's a coincidence going to massive brick sized heatsinks and common watercooling setups is what enabled current clocks, when it used to be exotic cooling territory.

(Regardless of tech or the underlying architecture behind it, even with the most exotic cooling, top clocks have stayed about the same)

Although, since those wires exist in current designs anyway, the effect on heat density may not be significant as some predict.

The design requirements for engineers without the tech must be a nightmare. BSPD/Power Via would be a huge relief.
 

DavidC1

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When TSMC goes HVM, products can typically start appearing ~6 months later (N5 was HVM in Q2 2020 and Apple had products on shelves with it by Fall 2020). It depends on when the products are ready though. N3B HVM was about 6 months late and so it missed the needed window for Apple to use it in 2022 and there weren't really any customers for it until Apple's fall refresh. Intel's products using it were still a bit ways away and everyone else waited for N3E.
I think the earliest will be Spring 2026 from other manufacturers.

You shouldn't feel bad for TSMC though. It's pretty much a rule in semiconductors for everyone to be delayed except in few exceptional cases. Even if 18A is better even compared to N2, no one switches to a supplier with near-zero credentials. If Intel expects significant foundry wins, it won't happen until they reach 2-3 year lead as they did previously while executing and delivering for years at the same time.

In reality they'll grow steadily and nowhere near their expectations by 2030 unless it's forced by external factors. The only factor that will influence it that significantly will render computers to be the LAST thing people care about.
 

SiliconFly

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I think the earliest will be Spring 2026 from other manufacturers.

You shouldn't feel bad for TSMC though. It's pretty much a rule in semiconductors for everyone to be delayed except in few exceptional cases. Even if 18A is better even compared to N2, no one switches to a supplier with near-zero credentials. If Intel expects significant foundry wins, it won't happen until they reach 2-3 year lead as they did previously while executing and delivering for years at the same time.

In reality they'll grow steadily and nowhere near their expectations by 2030 unless it's forced by external factors. The only factor that will influence it that significantly will render computers to be the LAST thing people care about.
Totally agree. It takes many many years to grow the customer base for foundries. Getting to 2nd place by 2030 itself is an extremely difficult task.
 

Hitman928

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I think the earliest will be Spring 2026 from other manufacturers.

Do you mean other chip designers? If so, then yeah, that was kind of my point. If N2 is ready by end of 2025, a company with a product on N2 could have products ready for sale by late spring or early summer 2026 if their designs were ready right when N2 went HVM. So I don't understand why you would say N2 is an H2 2026 product. . .

When Intel says a node is manufacturing ready, it seems they are talking about risk production at best and so you won't see products on that node (at volume) for at least a year after that point, probably longer.

You shouldn't feel bad for TSMC though. It's pretty much a rule in semiconductors for everyone to be delayed except in few exceptional cases. Even if 18A is better even compared to N2, no one switches to a supplier with near-zero credentials. If Intel expects significant foundry wins, it won't happen until they reach 2-3 year lead as they did previously while executing and delivering for years at the same time.

In reality they'll grow steadily and nowhere near their expectations by 2030 unless it's forced by external factors. The only factor that will influence it that significantly will render computers to be the LAST thing people care about.

It seemed like originally Intel was gearing up for 18a to bring in decent IFS business, but based upon the CEO and CFO's latest comments, it seems that goal is now pushed later towards the end of the decade and their shorter term goal is to get their internal designs off of needing TSMC silicon and back on completely Intel silicon. If true, it seems like they are banking on their product side to get their volume back up as well, otherwise they are going to be spending a lot of money on building out capacity that will be significantly under-utilized.
 

SiliconFly

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When Intel says a node is manufacturing ready, it seems they are talking about risk production at best...
Nope. When Intel says Manufacturing Ready, they mean volume production.

It seemed like originally Intel was gearing up for 18a to bring in decent IFS business
A few years in never enough to onboard new customers. The prime customer for 18A is Intel only. Others are low volume design from not so big customers. This should stem Intel Foundry losses from late 2025 onwards.
 

Hitman928

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Nope. When Intel says Manufacturing Ready, they mean volume production.

What is the quickest time for any product from Intel from the node being manufacturing ready to products on shelves with any kind of volume?

Edit: Even Intel admitted this in their latest fab press conference. The 18a node is "manufacturing ready" in 2024 but doesn't go HVM until 2025 and product volume doesn't actually ramp until 2026. This is from Intel themselves.
 
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oak8292

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Back when Intel was late on 14 nm and they showed notional yield curves they had a footnote that the yield curves were aligned with HVM and the definition was 1 million die in a quarter. That is not many wafers. When I did the math that was less than a FOUP per day. Intel started with U and Y die which are relatively small.

I am probably not right but I think PRQ on a new node takes it from R&D to manufacturing and in the past tax accounting made R&D dollars better than depreciation.
 

DavidC1

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Do you mean other chip designers? If so, then yeah, that was kind of my point. If N2 is ready by end of 2025, a company with a product on N2 could have products ready for sale by late spring or early summer 2026 if their designs were ready right when N2 went HVM. So I don't understand why you would say N2 is an H2 2026 product. . .
Because it's basically the unwritten rule for incredibly designs. Expect later than earlier, almost always. For the few times they got it earlier, many other times they did not. It's still basically Apple ramping their lineup.
When Intel says a node is manufacturing ready, it seems they are talking about risk production at best and so you won't see products on that node (at volume) for at least a year after that point, probably longer.
Not necessarily. Intel 3 may be a smaller change but Sierra Forest is just half a year behind. They got design side problems as well. An extreme example would be using Sapphire Rapids to say Intel 7 lead times are 2 years or something.