Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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[511]

FWIW Intel is the largest Synopsys customer

 

[Geddagod]

Using a combo of knowing die size from Techinsights (121.4mm2) + low rez die shot from yole group, you would get:
Tensor G5 X4: ~2.5mm2
Tensor G5 X725: ~0.91mm2
Unfort no one knows the L2 capacity for each core, so comparisons are not worth much.
~0.7mm2 is the area without what I think is just the L2 sram arrays, which is marginally smaller than the A720 in the 9400, and like ~20% smaller than than the A725 in the Xring O1. Though the A725's also clock ~10% faster in the Xring than the tensor G5.

 

[Doug S]

Apple uses latest Synopsys IP in their A19 SoCs. Qualcomm doesn’t. So it’s likely Apple or Intel

What do they use it for? I/O stuff like memory controllers or USB?

 

[poke01]

What do they use it for? I/O stuff like memory controllers or USB?