Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Ajay]

You can do both. You can increase sheet width till the gate length and scale the number of sheets too

Thanks for the links. Seems like doing both at the same time in a gen1 MBCFET process would be a recipe for disaster. IDK. Gen1 GAA xtor development seems to be a tough go. Good electrostatics, poor geometric gains. Hopefully the process engineers have some tricks for better shrinks is waiting on Gen2. Oh, duh, probably not enough High NA lithographs for HVM yet .

 

[maddie]

These new GAA designs are going to use a lot more fab steps, especially at the smallest feature levels. Each additional sheet vertically repeats itself in time as the 1st one, whereas additional fins could still take the same time to fabricate as lesser amounts. We won't have enough EUV machines for a long time.

 

[trivik12]

Looking at below chart N3 and N4P seem to offer similar performance/power figures. So there is little incentive to go for higher cost N3.

 

[Henry swagger]

You can do both. You can increase sheet width till the gate length and scale the number of sheets too

Timestamped videos from Samsung Semi

View attachment 63226View attachment 63227

This will bring big clock speeds 7ghz cpu's are close

 

[igor_kavinski]

This will bring big clock speeds 7ghz cpu's are close

Slow down, mate. Let us first get to 6 GHz

 

[moinmoin]

Looking at below chart N3 and N4P seem to offer similar performance/power figures. So there is little incentive to go for higher cost N3.

They'll have to rework this chart to include the five N3 variants...

 

[RTX]

So N2 is 1.15x N3E at 0.75 volts according to that picture.

https://images.anandtech.com/doci/17453/tsmc-n2-advantages-june-2022_575px.png

Is N3E 1.18x N5 at 0.75 volts?
This would mean N2 is 1.357x N5 at 0.75 volts, right?

Is N5 being compared to N7/N6 at 0.75 volts in TSMC's comparisons?

 

[Doug S]

Looking at below chart N3 and N4P seem to offer similar performance/power figures. So there is little incentive to go for higher cost N3.

You don't need to look at the chart, Anandtech has organized everything into a convenient table here.

You are overlooking that N4P offers 1.06x gain in logic density over N5, while N3 offers 1.7x. If your overall design scales more than N3 wafers cost more then N3 is of interest to you. Though most will wait for N3E which is gives back a bit of density but improves in performance, power and supposedly cost.

I haven't seen any recent estimates for N3 wafer cost, but one from back in 2020 indicated they would be about $3000 more than N5. N4/N4P is cheaper than N5, but probably not enough to matter, so we'll assume N4P costs the same as N5, so $3000 more is 15-20%.

I know some may look at the cost difference between N7 and N5 and say "no way the difference is only $3000" but looking at it cost wise TSMC eliminated a lot of multipatterning steps when they went from N7 to N7+ in a few layers, which is why the latter was cheaper. With N5 they switched the majority of layers to EUV, which didn't eliminate much in the way of multipatterning steps since they'd already done that with N7+ hence the rather large jump in wafer cost because all those EUV layers mean the use of expensive EUV scanners. N3 adds fewer EUV layers than N5 did, so it makes sense it would see a smaller price bump than N7->N5.

N3 designs should easily beat 15-20% in density even if they are cache heavy, so even after accounting for lower yields for N3 versus a mature member of the N5 family the per chip cost should be less. That's why you choose N3 over N4P, the few percent difference in performance and power is just icing on the cake. Obviously I'm talking a new design, if you have something already on N5 and want to keep making it largely unchanged you save a ton on design costs using N4P.

 

[Ajay]

They'll have to rework this chart to include the five N3 variants...

David Schor seems to be lagging a bit lately on publishing the latest news. IDK why.

 

[ashFTW]

David Schor seems to be lagging a bit lately on publishing the latest news. IDK why.

I’ve been concerned about him as well. I even messaged him on Twitter a while back. Hope he is ok!

Edit: His article is up!

A Look At Intel 4 Process Technology

A look at Intel's next-generation high-performance process technology, Intel 4.

fuse.wikichip.org

 

[igor_kavinski]

https://twitter.com/x/status/1538849541188997121

Hmm...N4 seems to be looking very good.

 

[igor_kavinski]

Legendary Chip Architect, Jim Keller, Says AMD 'Stupidly Cancelled' K12 ARM CPU Project After He Left The Company (wccftech.com)

Wow. Saying that publicly can only mean he's pissed at AMD.

 

[Doug S]

https://twitter.com/x/status/1538849541188997121

Hmm...N4 seems to be looking very good.

That's hardly surprising, since N4 is a tweaked N5. There's no way it should start out any other way that well below N5's defect rate.

 

[Ajay]

Legendary Chip Architect, Jim Keller, Says AMD 'Stupidly Cancelled' K12 ARM CPU Project After He Left The Company (wccftech.com)

Wow. Saying that publicly can only mean he's pissed at AMD.

Meh. Sour grapes don't look good on anyone, even Keller.

 

[igor_kavinski]

Meh. Sour grapes don't look good on anyone, even Keller.

He shouldn't have left his baby in the care of others. Should have stayed till K12 launched.

 

[Roland00Address]

This will bring big clock speeds 7ghz cpu's are close

But why?

I am half serious, you are still going to have the dark silicon problem where there is still going to be limits of how much power you can pipe into very small subsections of the chip (aka input), and have problems cooling it (aka output.)

The technology is still great do not get me wrong, but for efficiency reasons other things this same tech does like reducing leakage can increase performance and reduce power consumption, but hitting a magical number of ghz may still not happen.

Legendary Chip Architect, Jim Keller, Says AMD 'Stupidly Cancelled' K12 ARM CPU Project After He Left The Company (wccftech.com)

Wow. Saying that publicly can only mean he's pissed at AMD.

He, Jim, is what 63ish years old? If he goes to different companies every 2 to 4 years (I think the longest company he worked for was around 5 years), then he may not have many more rodeos inside of him even if he is still brilliant*

*I assume he is, but also label this assumption for I have no first hand knowledge.

 

[Doug S]

Interesting article at Semianalysis suggesting that making stuff out of chiplets doesn't necessarily reduce costs, depending on the dimensions of the chiplets.

Now obviously the designers know this and would presumably try to avoid doing something like his (freely admitted to be) rather contrived example. But I guess we should expect most designs that in the 100+ mm^2 range will be either 16.5 or 8.25 mm wide in the high NA era.

https://semianalysis.substack.com/p/die-size-and-reticle-conundrum-cost

 

[DrMrLordX]

He shouldn't have left his baby in the care of others. Should have stayed till K12 launched.

Zen had an entire team behind it, with Mike Clark being a major player. It's not entirely clear what parts of that team were also involved in the development of K12 or how much influence they (or Keller) had in releasing products based on it or in continuing development. It's possible that AMD decided to shelve K12 permanently regardless of what Keller had to say about it. Which may be one of the reasons why he left.

In retrospect, it might not have been a poor decision. ARM has launched its own server-first designs that anyone can license, which everyone cribs from for enterprise ARM products. Er well everyone except maybe Huawei with their Kunpeng designs. But Kunpeng has been locked up behind embargos, and it may not amount to much anyway, outside of the PRC.

Regardless, that's an environment that's fairly hostile to K12. Even if K12 and successive designs had proven to be superior to, say, Graviton 2 or Altra/Altra MAX, AMD would still be facing the same uphill battle of software compatibility faced by all the other ARM server vendors. On top of that, there's the issue of dealing with competition available for license from ARM, Ltd. With x86, AMD only has to worry about Intel. x86 offers a larger customer base. Maybe someday AMD will revisit the K12 frontend, and update their leading-edge designs to incorporate something similar. Or maybe not. We'll see.

 

[moinmoin]

Interesting article at Semianalysis suggesting that making stuff out of chiplets doesn't necessarily reduce costs, depending on the dimensions of the chiplets.

Now obviously the designers know this and would presumably try to avoid doing something like his (freely admitted to be) rather contrived example. But I guess we should expect most designs that in the 100+ mm^2 range will be either 16.5 or 8.25 mm wide in the high NA era.

https://semianalysis.substack.com/p/die-size-and-reticle-conundrum-cost

That's somewhat contrived and overly long indeed. But its main point stands: there are different aspects to the total cost, and the more the resulting product is optimized to them the cheaper can it be made, with the reverse being equally true.

In this article the focus is on the photo mask being 104mm by 132mm which can print a field of 26mm by 33mm. The less space a particular die design leaves unused of that reticle the cheaper the lithography production step.

 

[leoneazzurro]

About Keller: AMD at the time had barely the money to sustain one line of processors. Nowadays they said that if the market asks to produce ARM CPus, thay can. Especially after the Xilinx acquisition. Seeing a project you worked on cancelled is always a bad thing for an engineer, however a company cannot everytime do everything. There are budget, choices. And seeing AMD now, I think no one can say that this management is lacking.

 

[Frenetic Pony]

That's somewhat contrived and overly long indeed. But its main point stands: there are different aspects to the total cost, and the more the resulting product is optimized to them the cheaper can it be made, with the reverse being equally true.

In this article the focus is on the photo mask being 104mm by 132mm which can print a field of 26mm by 33mm. The less space a particular die design leaves unused of that reticle the cheaper the lithography production step.

It's pretty artificial to come to the conclusions he wants. He only cuts the dies in half, and then with a really bad aspect ratio instead of near square for a chiplet, underselling the advantage of chiplets just in terms of yield. Also assumes all defetive dies must be tossed, again advantaging monolithic as smaller dies are more likely to be salvageable due to lower incidence of overlapping errors. Not to mention not going for yet more and smaller chiplets, which would still scale up the yields yet further. He also fits the die sizes to exactly fit his talking points he's already decided for illustration purposes, look this die doesn't have good reticle utilization, oh if only I'd not designed it to have exactly this fault! Thus all chiplets are expensive. Yet every last major chip designer is going chiplets, AMD already claims it's saving a good deal with Zen chiplets and has done so for a while. Maybe because these companeis know how to optimize for lithography constraints with their foundry to still make chiplets more profitable than monolithic. Maybe ASML and other will do their best to adapt their tools over time to better serve chiplet arches and quite possibly already have.

What a silly article. If it had been short and "be careful when designing chiplets because there's extra constraints dealing with cost" it would've been a lot better. Not that this is the first utterly silly conclusion he's come to. Doomsaying over ever increasing costs destroying the industry, even as now (just like two months later) DDR prices are dropping due to oversupply, and DDR5's cost premium should drop once power ICs get back to a good supply as well, as just one example.

 

[ashFTW]

However, differentiating tech on N3. FinFlex.
View attachment 63194

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Mixing and matching two fin and three fin together in one die, this is awesome. e.g. 2-1 Fin on L3 and 2-2 Fin on logic, sounds like a dream come true for cache heavy designs, or almost. L3 would be well suited running on a different clock domain from the core.

View attachment 63197

View attachment 63196

This time TSMC is also a bit more realistic with the numbers, when estimating a high performance SoC, 50% logic, 30% SRAM and 20% analog. In the past they are more logic heavy in their estimation.
Two additional nodelets added,
N3S --> density optimized
N3P --> Performance optimized.

Doing FinFlex without back side power delivery should be quite challenging due to differential placement of power rails for the different sized cells. Kudos to TSMC!

Once we have Gate-all-around with N2, lets see if transistors with different characteristics will still be supported (by varying the number of nanosheets and their width) on the same chip. There won’t be any density benefits, only performance/efficiency gains.

 

[Ajay]

There won’t be any density benefits, only performance/efficiency gains.

Why is that?

 

[ashFTW]

Why is that?

The nano sheets are stacked on top of each other, so varying their number changes Z dimension but doesn’t change the XY area occupied by the transistor.

 

[Ajay]

The nano sheets are stacked on top of each other, so varying their number changes Z dimension but doesn’t change the XY area occupied by the transistor.

So, doesn’t that improve density? You can get the performance you need out of the xtor by building it taller (Z), rather than adding more fins in the XY dimension.