Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[DrMrLordX]

This is from WSJ article that we are hitting Supply issues on leading edge. Probably will impact everyone but Apple is the least likely to be impacted as they get the 1st bite of all leading edge nodes. This could be why I could see 3nm missing until 2024.

Isn't Intel going to actually get some of the earliest N3 wafers?

 

[Doug S]

Isn't Intel going to actually get some of the earliest N3 wafers?

Unless something surprising happens, like A16 being built on N3 risk production wafers, or the M2 Pro/Max die coming out next year and going on N3, I don't see how Intel doesn't get the earliest wafers. If as is likely neither of those things happens Apple won't ship devices with N3 chips until Sept. 2023. Maybe a couple months earlier if M3 is only a 12 month gap from M2.

 

[DisEnchantment]

Summary of Intel 4 from David Kanter.

Intel 4 Process Scales Logic with Design, Materials, and EUV - Real World Tech

The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography. The first product, the Meteor Lake compute tile, will ramp to high volume...

www.realworldtech.com

Scaling seems conservative on Intel 4 (compared to Intel's cadence but in line with TSMC's generational gains, albeit with TSMC updating their process more frequently), granted this is for HP cells
From this table below, we can calculate density to be quite less than the 2x scaling.



Surprisingly using SAQP on M0 and SADP on M1 onwards.

However, in an ironic twist the only sub-40nm pitch metal layer, the 30nm M0, is still formed using SAQP .

Finally dropped the troublesome Co layers too.

However, I find it surprising they used 4 fins on Intel 7. No wonder they tanked hard on efficiency
In contrast, AMD is using 2 fin cells with relaxed densities on N7. TSMC N7 manage to have almost comparable transistor performance vs Intel 7 even going with 2 Fin vs 4 Fin.

2 Fin HD cell being available on Intel 3 is probably the reason they are offering it for IFS not Intel 4.
Efficiency wise should be a big gain for Intel, finally. Better late than never.
Interesting thing is that they are jumping directly to GAA instead of another FinFET node.
Since Intel 3 does not look like a substantial improvement besides adding the HD libs, TSMC will keep the lead in device performance and efficiency and density with N3 and N3E.
Remains to be seen in comparison with N3, which entered risk production in 1Q22.

Not sure if Intel will use the 2 Fin version of Intel 3, since they might lose clocks (but gain density and efficiency greatly).

 

[ashFTW]

Since Intel 3 does not look like a substantial improvement besides adding the HD libs, TSMC will keep the lead in device performance and efficiency and density with N3 and N3E.

From DK’s article:

”The second step is creating the follow-on Intel 3 process by adding features to support more designs, improve density, and significantly enhance performance. According to the company, the Intel 3 node will improve performance by 18% over Intel 4. This is equivalent to the performance gain for a full node transition; comparable to the Intel 7 to Intel 4 transition and slightly greater than the TSMC 7nm to 5nm transition.”

 

[DisEnchantment]

”The second step is creating the follow-on Intel 3 process by adding features to support more designs, improve density, and significantly enhance performance. According to the company, the Intel 3 node will improve performance by 18% over Intel 4. This is equivalent to the performance gain for a full node transition; comparable to the Intel 7 to Intel 4 transition and slightly greater than the TSMC 7nm to 5nm transition.”

I missed most of the changes from N3 Intel 3. I have not seen the density gains though. If that is the case it is quite impressive.

 

[ashFTW]

I missed most of the changes from N3. I have not seen the density gains though. If that is the case it is quite impressive.

David Schor @ WikiChip, whom I respect a Lot, seems to think so as well.

https://twitter.com/x/status/1536170730164998145

 

[DrMrLordX]

Finally dropped the troublesome Co layers too.

Check out the eCu. There's some cobalt in there.

 

[LightningZ71]

How are they going to achieve relevant volume with the well known lack of EUV machines that they face? Are they going to be restricted to tiny chips one one or two lines for maximum volume and count on being able to use tiles to cover the needs of the rest of the SoC?

 

[mikk]

Enhanced copper means cobalt-clad copper.

For Intel 4, in turn, Intel is taking half a step back. The company is still using cobalt in their processes, but now rather than pure cobalt they are using what they are calling Enhanced Copper (eCu), which is copper cladded with cobalt. The idea behind eCu is to have the best of both words, maintaining the performance of a doped copper metallization layer, while still getting the electromigration resistance benefits of cobalt.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

The I4 process uses an 'enhanced copper' design that leverages a tantalum barrier with cobalt cladding over pure copper. This design provides the best of both performance and reliability.

https://www.tomshardware.com/news/intel-debuts-meteor-lake-die-intel-4-node-20-higher-clocks-at-same-power-2x-area-scaling

 

[ashFTW]

Another good article on Intel 4 by Scotten Jones @ SemiWiki.

Conclusion: ”I am very impressed with this process. The more I compare it to offerings from TSMC and Samsung the more impressed I am. Intel was the leader in logic process technology during the 2000s and early 2010s before Samsung and TSMC pulled ahead with superior execution. If Intel continues on-track and releases Intel 3 next year they will have a foundry process that is competitive on density and possibly the leader on performance.”

Intel 4 Deep Dive - Semiwiki

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12). “Intel 4 CMOS...

semiwiki.com

 

[DisEnchantment]

Ouch, that N2 scaling with GAA

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

However, it seems similar to Samsung's numbers for GAA transition. Solid perf and power reductions but minor density gains.

Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

https://news.samsung.com/global/sam...of-big-data-ai-ml-and-smart-connected-devices

Density not so critical, but the power savings are really substantial though.

Seems Samsung might have a shot at catching up to TSMC on GAA, they have 3 years to fix yields and improve the process until TSMC launch their GAA process and two years until Intel launch theirs.
Good thing, seems their suppliers (Applied Materials) seem confident of fixing the issues, and on top of that their PDK already got certified.

Quadra is not so far away, lets see what it turns out to be.

 

[DisEnchantment]

However, differentiating tech on N3. FinFlex.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

Mixing and matching two fin and three fin together in one die, this is awesome. e.g. 2-1 Fin on L3 and 2-2 Fin on logic, sounds like a dream come true for cache heavy designs, or almost. L3 would be well suited running on a different clock domain from the core.





This time TSMC is also a bit more realistic with the numbers, when estimating a high performance SoC, 50% logic, 30% SRAM and 20% analog. In the past they are more logic heavy in their estimation.
Two additional nodelets added,
N3S --> density optimized
N3P --> Performance optimized.

 

[Exist50]

Mixing and matching two fin and three fin together in one, this is awesome.

Small correction, but it looks like it goes [gate count]-[fin count], at least according to the Anandtech article.

But yeah, the N2 scaling seems pretty poor, especially since it's in relation to N3E. If N2 also lasts 3 years, that will be a long time without any significant density gains.

 

[moinmoin]

Ouch, that N2 scaling with GAA
View attachment 63192

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

However, it seems similar to Samsung's numbers for GAA transition. Solid perf and power reductions but minor density gains.


https://news.samsung.com/global/sam...of-big-data-ai-ml-and-smart-connected-devices

Density not so critical, but the power savings are really substantial though.

Seems Samsung might have a shot at catching up to TSMC on GAA, they have 3 years to fix yields and improve the process until TSMC launch their GAA process and two years until Intel launch theirs.
Good thing, seems their suppliers (Applied Materials) seem confident of fixing the issues, and on top of that their PDK already got certified.

Quadra is not so far away, lets see what it turns out to be.

I guess we have a simple case of GAA being more complex than FinFET so the reasonable way would actually be to reduce density first to get it up an running and increase it from there. But can't have that so it gets delayed and still looks bad for the first gen.

That said if Samsung can't capitalize on its time advantage at this crucial point it will never get ahead.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

Five different versions of N3 now already? Ooof...

 

[Saylick]

Five different versions of N3 now already? Ooof...

Inb4 N3++++ jokes.

 

[Doug S]

Ouch, that N2 scaling with GAA
View attachment 63192

Well the 1.3x for N3 to N5 is listed as 1.6x for logic. Putting 20% analog in there is really interesting, your typical CPU isn't going to have anything like that much. Why not just do what they did last time and list the scaling for logic and cache separately?

Given that N2 is supposed to introduce backside power delivery, I'm a little surprised the numbers aren't better simply because that ought to help with cache scaling. Maybe BPD doesn't come in the first cut of N2, or it needs the next step beyond that (can't remember what that's called, but it is basically a further evolution of backside power delivery that really helps with wire routing through the metal layers)

There's always the possibility they are sandbagging with that ">". A lot of people seemed ready to believe that with AMD's Zen 4 numbers, and I'd argue that TSMC has lot more reason to sandbag about something that's three years away if they don't want to tip their hand to the competition just yet, than AMD would have for something that's three months away.

 

[dttprofessor]

Who is the first client for N3？

 

[Frenetic Pony]

Ouch, that N2 scaling with GAA
View attachment 63192

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

However, it seems similar to Samsung's numbers for GAA transition. Solid perf and power reductions but minor density gains.


https://news.samsung.com/global/sam...of-big-data-ai-ml-and-smart-connected-devices

Density not so critical, but the power savings are really substantial though.

Seems Samsung might have a shot at catching up to TSMC on GAA, they have 3 years to fix yields and improve the process until TSMC launch their GAA process and two years until Intel launch theirs.
Good thing, seems their suppliers (Applied Materials) seem confident of fixing the issues, and on top of that their PDK already got certified.

Quadra is not so far away, lets see what it turns out to be.

Density scaling is becoming progressively less important. Haven't gotten any transistor cost scaling for a while now, there are cost savings from smaller chips in other ways but you can get that from chiplets nigh as well as any density scaling. Design companies will still pay if they can deliver power and performance scaling as indicated.

Who is the first client for N3？

Saw speculation based on product timelines that someone might beat Apple to it. But the gains of N3 over N4P appear almost non existent so I'm not sure Apple, who doesn't generally advertise "lame nerd stuff" like "technical" numbers as much as their competitors, cares. Wouldn't be surprised if N3E were created, and moved up, in part to get Apple's business after N3 was deemed to not be worth it.

 

[DisEnchantment]

Small correction, but it looks like it goes [gate count]-[fin count], at least according to the Anandtech article.

Thanks, sloppy writing on my part.

But yeah, the N2 scaling seems pretty poor, especially since it's in relation to N3E. If N2 also lasts 3 years, that will be a long time without any significant density gains.

I believe, this would impact mobile more than it would to HPC.
Because for HPC it means increasing sheet count in the Z dimension, instead of increasing fin count in Y dimension
Density would be same across HPC and mobile, with sheet count and width being customized (in the z dimension).
HPC could regain the absolute density offered by N3 while not compromising on performance.

At this point it is unknown what happens to the routing in the Metal layers.

 

[Doug S]

Who is the first client for N3？

It is unclear, but it would appear to be Intel. If Apple is building M2 on N5P and A16 on N4, they wouldn't have anything for N3 until middle of next year when A17 ramps up...other than maybe Apple Watch which isn't exactly high volume.

 

[moinmoin]

Density scaling is becoming progressively less important. Haven't gotten any transistor cost scaling for a while now, there are cost savings from smaller chips in other ways but you can get that from chiplets nigh as well as any density scaling. Design companies will still pay if they can deliver power and performance scaling as indicated.

It may become less important, but we definitely are not there yet. Chip designers still use increased density awarded through node jumps to pack more features within the same space. Once density stagnates Moore's law is truly over and new features will have to be balanced with existing features, either trading existing areas or increasing die size, thus decreasing yield.

 

[ashFTW]

It is unclear, but it would appear to be Intel. If Apple is building M2 on N5P and A16 on N4, they wouldn't have anything for N3 until middle of next year when A17 ramps up...other than maybe Apple Watch which isn't exactly high volume.

Isn’t Apple rumored to use N3 for M2Pro, and M2Max. And these chips may be released end of ‘22, or early ‘23, before anything Intel on N3.

 

[Doug S]

Isn’t Apple rumored to use N3 for M2Pro, and M2Max. And these chips may be released end of ‘22, or early ‘23, before anything Intel on N3.

As with M1 rumors are all over the place so I don't give them much credence. If they use a whole different process, why not also use a newer design (i.e. A16 cores) and at that point why would it still be called "M2" instead of calling it "M3"?

I mean, no rule says that M2 HAS to have a Pro/Max, and that Pro/Max can't be released for M3 before the regular M3. Or that there would even be a regular M3, as maybe you see M4 in before the 2023 holidays based on the A17 core?

I'm just throwing these out as reasonable possibilities, but there are many, with absolutely no way to tell guess what Apple is actually planning.

I will say the possibility of something A16 based built on N3 would go along with the rumor of A16 being in the Pro line of iPhones only. If it was primarily designed for N3 it would be rather large on N4 and Apple would have incentive to limit it to higher priced iPhones due to its higher cost.

 

[Ajay]

I believe, this would impact mobile more than it would to HPC.
Because for HPC it means increasing sheet count in the Z dimension, instead of increasing fin count in Y dimension
Density would be same across HPC and mobile, with sheet count and width being customized (in the z dimension).
HPC could regain the absolute density offered by N3 while not compromising on performance.

At this point it is unknown what happens to the routing in the Metal layers.

Huh, I thought the opposite. That HP GAA would use fewer, wider sheets to reach the required higher currents and that HD designs would use a process variant that stacks numerically higher, narrow sheets for maximum density.

Additionally, it seems like width increases would be more geometricly stable, but IDK for sure. There as a more recent article on Samsung N3 GAA, but I can’t seem to find it.

 

[DisEnchantment]

Huh, I thought the opposite. That HP GAA would use fewer, wider sheets to reach the required higher currents and that HD designs would use a process variant that stacks numerically higher, narrow sheets for maximum density.

Additionally, it seems like width increases would be more geometricly stable, but IDK for sure. There as a more recent article on Samsung N3 GAA, but I can’t seem to find it.

You can do both. You can increase sheet width till the gate length and scale the number of sheets too

Timestamped videos from Samsung Semi

One advantage of MBCFET is that additional area is not required to improve speed. FinFETs need fins to be laterally added while Nanosheets can be vertically stacked