Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[moinmoin]

We don't know the decisions and compromises AMD makes. But we know that in the cases AMD did publicly mention which library it uses that it was the one focused on high density, not high performance.

There keeps being reports about AMD using some custom process which I personally consider rather unfeasible in the true meaning of "process". But what I consider likely is that AMD keeps using high density libraries for basing their designs on the smallest possible grid pattern to work with, and have an ongoing exchange with TSMC about optimizations possible for achieving the highest possible frequency. AMD then applies this knowledge selectively in its designs while TSMC accordingly optimizes its HPC process variant for general use.

 

[DrMrLordX]

What makes you think every device characteristics has no compromise, is there special thing that other Designers do not know

I never said that was the case. AMD understands what comes from using 6 instead of 7.5. Rethink your statements.

 

[DisEnchantment]

I never said that was the case. AMD understands what comes from using 6 instead of 7.5. Rethink your statements.

You're the one making claim about a highly coveted (even by the likes of Apple) AMD variant of N5. Do you think these folks don't know what they are doing with N5. They have to look up to an AMD variant?
Think about it.

 

[DisEnchantment]

We don't know the decisions and compromises AMD makes. But we know that in the cases AMD did publicly mention which library it uses that it was the one focused on high density, not high performance.

There keeps being reports about AMD using some custom process which I personally consider rather unfeasible in the true meaning of "process". But what I consider likely is that AMD keeps using high density libraries for basing their designs on the smallest possible grid pattern to work with, and have an ongoing exchange with TSMC about optimizations possible for achieving the highest possible frequency. AMD then applies this knowledge selectively in its designs while TSMC accordingly optimizes its HPC process variant for general use.

Indeed, we don't know, that is the point.
We do know only what we know and that is all the characteristics advertised by TSMC has tradeoffs, either this or that. They themselves said it.
When Apple choose whatever they choose they know what they want, and their design is not made to clock 5GHz they target the device characteristics accordingly
David Schor ( from IEDM presentation by TSMC ) said there are two main TSMC process variants on N5, regular and HPC variant with additional scaling boosters
A newer version of N5 exists called N5P.
From IC Insight analysis of Zen2, it is plain N7 HD trading off density heavily and improved BEOL for higher frequency.

Other designers know what frequency they target, what efficiency they want and what knobs to tweak, and TSMC is there to help them do just that.

 

[DrMrLordX]

You're the one making claim about a highly coveted (even by the likes of Apple) AMD variant of N5.

Just repeating a claim made elsewhere (same source basically said, AMD will be getting 20kwpm N5, which seems low but maybe isn't). The word is already going around.

Do you think these folks don't know what they are doing with N5. They have to look up to an AMD variant?
Think about it.

No, and they don't "have to" but if they want 6t libraries with relaxed gate pitch then Bob's your uncle. At least that's what AMD apparently got from TSMC on N7 with Zen2 and Zen3. They did very well with it, too. Why Apple would choose the same at this point is anyone's guess. It's also not clear which product would ship on this "custom" node.

Also there are no indications (yet) of AMD using N5P for Zen4. A15 is supposed to be using N5P. M2 is also supposed to have taped out on N5P.

 

[Doug S]

There keeps being reports about AMD using some custom process which I personally consider rather unfeasible in the true meaning of "process". But what I consider likely is that AMD keeps using high density libraries for basing their designs on the smallest possible grid pattern to work with, and have an ongoing exchange with TSMC about optimizations possible for achieving the highest possible frequency. AMD then applies this knowledge selectively in its designs while TSMC accordingly optimizes its HPC process variant for general use.

It would be interesting to know more about this. I wonder if AMD/TSMC would be forthcoming if someone like Andrei questioned them, or it would be treated as some sort of trade secret?

There's a lot of room to interpret "custom process". Are they talking tweaks to create e.g. taller and thinner fins? (which would be my guess) Is it a change in the metal stack? Something else? There are some "custom" things (like changes to the metal stack) that would basically require a line basically dedicated to AMD, as the process flow would be very different for their wafers. If AMD commits to buying in sufficient numbers to justify perhaps that is possible? I have no idea how many wpw you're talking for a minimum "line" unit in a modern fab on a leading edge process though, a dedicated line may be completely infeasible and if it were would not only require purchasing in "sufficient numbers" it would likely also preclude increasing orders if AMD had greater demand than forecast.

 

[Roland00Address]

Sorry did not see the comment was old. Where is the delete post button?

 

[DisEnchantment]

Quick Summary of TSMC Fab Locations/Maps annotated by me based on TSMC presentations (paywalled somewhere) but satellite maps are outdated ... from early 2021

N5 [EUV] Tainan Science Park, Tainan
F18P1 - In Production
F18P2 - In Production
F18P3 - In Production
F18P4 - In Production Q122/risk production for N3

N3 [EUV]- Tainan Science Park, Tainan
F18P5 - Equipping , full production in late 22/Early 23
F18P6 - Equipping , full production in late 22/Early 23
F18P7 - Under construction
F18P8 - Under construction

N7 [DUV] - Tainan Science Park, Tainan , next to N5/3 fabs
F14P1/2/3/4/5/6/7 in Production
F14P8 - Under construction
Converting to EUV/N6

N7+/N6 [EUV] Central Taiwan Science Park Taichung
F15P5/6/7/?/? - In Production

N2
Fab 20 - Land to be acquired, construction will start in late 2022/2023

All in all N7/N6 capacity will be around 220K to 240K wpm once F14P8 is online (the original F14 fabs were designed around 20K wpm each phase)
N5 capacity should be 100 to 120K wpm in 2022
F18 and Arizona fabs are designed for 30K+ and Daniel Nenni is saying they are actually upgrading to output 40K wpm each phase

I wanna do one like this for Samsung, but data is harder to find

Fab 18 and Fab 14 Tainan Science Park, Tainan


F18P8 on Mid 2021, you will notice another plot of F14P8 as well.

Spoiler: FAB15

Spoiler: FAB20

 

[Ajay]

Quick Summary of TSMC Fab Locations/Maps annotated by me based on TSMC presentations (paywalled somewhere) but satellite maps are outdated ... from early 2021

N5 [EUV] Tainan Science Park, Tainan
F18P1 - In Production
F18P2 - In Production
F18P3 - In Production
F18P4 - In Production Q122/risk production for N3

N3 [EUV]- Tainan Science Park, Tainan
F18P5 - Equipping , full production in late 22/Early 23
F18P6 - Equipping , full production in late 22/Early 23
F18P7 - Under construction
F18P8 - Under construction

N7 [DUV] - Tainan Science Park, Tainan , next to N5/3 fabs
F14P1/2/3/4/5/6/7 in Production
F14P8 - Under construction
Converting to EUV/N6

N7+/N6 [EUV] Central Taiwan Science Park Taichung
F15P5/6/7/?/? - In Production

N2
Fab 20 - Land to be acquired, construction will start in late 2022/2023

All in all N7/N6 capacity will be around 220K to 240K wpm once F14P8 is online (the original F14 fabs were designed around 20K wpm each phase)
N5 capacity should be 100 to 120K wpm in 2022
F18 and Arizona fabs are designed for 30K+ and Daniel Nenni is saying they are actually upgrading to output 40K wpm each phase

I wanna do one like this for Samsung, but data is harder to find

Fab 18 and Fab 14 Tainan Science Park, Tainan
View attachment 53878

F18P8 on Mid 2021, you will notice another plot of F14P8 as well.
View attachment 53880

Spoiler: FAB15

View attachment 53879

Spoiler: FAB20

View attachment 53881

Great Job! Is this what you do to relax

 

[uzzi38]

Seems like N3 potentially might be worth it if you're willing to put in the effort with DTCO?

I don't like how TSMC didn't include N7 and N5 DTCO charts here though, we've already seen how mich of effect it can have (RDNA1 -> RDNA2).

 

[moinmoin]

Is DTCO even something that can be compared at node level? From what I'm aware of DTCO (Design and Technology Co-optimization) is a feedback progress the customer has to be willing to apply during silicon design to make the most of the node. With today's costly nodes I rather have to wonder who still doesn't do that at least to some degree.

 

[Ajay]

Is DTCO even something that can be compared at node level? From what I'm aware of DTCO (Design and Technology Co-optimization) is a feedback progress the customer has to be willing to apply during silicon design to make the most of the node. With today's costly nodes I rather have to wonder who still doesn't do that at least to some degree.

This is what the Apple/TSMC partnership has been about. Now, companies like Synopsis have built tool chains that support this process in an automated system resulting in improvements in productivity and better integration. At least as far as I can tell.

 

[jpiniero]

TSMC Introduces N4X Process|Taiwan Semiconductor Manufacturing Company Limited

HSINCHU, Taiwan, R.O.C., Dec. 16, 2021 – TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4X process technology, tailored for the demanding workloads of high performance

pr.tsmc.com

TSMC has another refresh of their 5 nm node they are calling N4X. Says risk production in the first half of 2023. Mainly geared toward higher frequencies.

 

[Ajay]

TSMC Introduces N4X Process|Taiwan Semiconductor Manufacturing Company Limited

HSINCHU, Taiwan, R.O.C., Dec. 16, 2021 – TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4X process technology, tailored for the demanding workloads of high performance

pr.tsmc.com

TSMC has another refresh of their 5 nm node they are calling N4X. Says risk production in the first half of 2023. Mainly geared toward higher frequencies.

Wow, this is such a small incremental change! I guess some large customer wanted that or it wouldn't exist.

 

[igor_kavinski]

Wow, this is such a small incremental change! I guess some large customer wanted that or it wouldn't exist.

The Future is Now - Taiwan Semiconductor Manufacturing Company Limited (tsmc.com)

• Up to 15% performance boost over N5 (at supply voltage of 1.2V) – transistor performance as a function of voltage is optimized, with a slight tradeoff in leakage current

"We made it faster but it'll also run a bit hotter. "

Definitely gonna end up powering a supercomputer somewhere.

UNLESS, AMD decides to follow Intel's lead in making expensive den "heaters".

 

[Hitman928]

The Future is Now - Taiwan Semiconductor Manufacturing Company Limited (tsmc.com)



"We made it faster but it'll also run a bit hotter. "

Definitely gonna end up powering a supercomputer somewhere.

UNLESS, AMD decides to follow Intel's lead in making expensive den "heaters".

It's 15% over N5 but only 4% faster than N4P. However, TSMC is saying that N4X FETs are also qualified to run at higher voltages than N5 or N4P and so you can get even more frequency by 'overdriving' the FETs. Obviously expect that power consumption will go up even more. The only 2 companies that I can think of that would ask for something like this would be IBM or Intel. They are the only ones who are still trying to push frequencies as far as possible and don't seem to care as much about power consumption. AMD could of course use it as well, but that seems to go against their recent history.

 

[DisEnchantment]

It's 15% over N5 but only 4% faster than N4P. However, TSMC is saying that N4X FETs are also qualified to run at higher voltages than N5 or N4P and so you can get even more frequency by 'overdriving' the FETs. Obviously expect that power consumption will go up even more. The only 2 companies that I can think of that would ask for something like this would be IBM or Intel. They are the only ones who are still trying to push frequencies as far as possible and don't seem to care as much about power consumption. AMD could of course use it as well, but that seems to go against their recent history.

The device performance coming with tradeoff in leakage and higher drive currents may not be so desirable for AMD.
But this item below should be important for high clock x86 designs, not sure if it will make as much difference in lower clocked/voltage ARM smartphone SoCs.

Lower resistance and parasitic capacitance of targeted metal layers - back-end-of-line metal layer optimization greatly affects HPC products, due to larger die sizes, higher clock frequencies, and higher operating voltages

The Future is Now - Taiwan Semiconductor Manufacturing Company Limited

Evolving Computing Landscape When I worked for a big corporate executive in charge of mainframe business in the early 2000s, we spent a lot of time visiting Fortune100 CIOs in New York City. And while mainframes still are strategically critical today, I look back and realize how rapidly the...

www.tsmc.com

Could be something AMD already did with their "HPC optimized N5 process" but should be super useful if they can cherry pick this.

 

[Doug S]

N4X is kind of an odd duck. Only 4% faster than N4P and therefore slower than N3, but with risk production starting in H1 2023 it wouldn't be ready for mass production until maybe a year after N3 hits mass production.

I guess as an offshoot of N5 it would be well depreciated by 2024 and thus cost quite a bit less than N3. I wonder if N4X started as sort of a custom process for AMD and evolved into an official TSMC process offering?

 

[Saylick]

AMD already advertised a 25% performance increase, independent of architecture, for Zen 4 through the use of some TSMC N5-based HPC node. According to the plot, N5 HPC is about 10% faster than standard N5. If N4X is only 15% faster than standard N5, that's really not much of an improvement to go from N5 HPC to N4X. If anything, seems like N4X is just a refined version of N5 HPC where they've rebranded HPC to X.

 

[uzzi38]

The Future is Now - Taiwan Semiconductor Manufacturing Company Limited (tsmc.com)



"We made it faster but it'll also run a bit hotter. "

Definitely gonna end up powering a supercomputer somewhere.

UNLESS, AMD decides to follow Intel's lead in making expensive den "heaters".

You do realise AMD have said on multiple occasions that Zen 3 uses custom modified (by AMD) libraries, right?

What makes you think they're going to just stop with the DTCO?

 

[jpiniero]

It's 15% over N5 but only 4% faster than N4P. However, TSMC is saying that N4X FETs are also qualified to run at higher voltages than N5 or N4P and so you can get even more frequency by 'overdriving' the FETs. Obviously expect that power consumption will go up even more. The only 2 companies that I can think of that would ask for something like this would be IBM or Intel. They are the only ones who are still trying to push frequencies as far as possible and don't seem to care as much about power consumption. AMD could of course use it as well, but that seems to go against their recent history.

nVidia perhaps? Could maybe work as a high performance ARM desktop processor?

 

[moinmoin]

I wonder if N4X started as sort of a custom process for AMD and evolved into an official TSMC process offering?

I can imagine that to be the case with all optimized nodes at TSMC, them essentially being best practice collections of previous "custom processes" for customers to pick up that don't want to go into the nitty gritty of DTCO themselves.

 

[Hitman928]

nVidia perhaps? Could maybe work as a high performance ARM desktop processor?

Maybe but I don't think it is likely. If Nvidia tries to step back into the consumer CPU space I think it's much more likely to start in the mobile or laptop spaces rather than jump straight into a market where ARM is non-existent. Maybe a super high performance server CPU to go along with their HPC GPU offerings, but again, I find that highly doubtful given the current lack of ARM ecosystem in that space as well as the all the baggage that comes with trying to start a server line of processors.

 

[uzzi38]

AMD already advertised a 25% performance increase, independent of architecture, for Zen 4 through the use of some TSMC N5-based HPC node. According to the plot, N5 HPC is about 10% faster than standard N5. If N4X is only 15% faster than standard N5, that's really not much of an improvement to go from N5 HPC to N4X. If anything, seems like N4X is just a refined version of N5 HPC where they've rebranded HPC to X.

It's not just the performance difference that stands out. N5 HPC is 2x the leakage of other N5 libs, which is also rather obviously not in line with AMD's figures.

 

[Saylick]

It's not just the performance difference that stands out. N5 HPC is 2x the leakage of other N5 libs, which is also rather obviously not in line with AMD's figures.

So you're saying AMD is using some kind of node with the performance of N5 HPC but without the leakage?